# US 12,190,953 B2 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,190,953 B2 - Document ID: US12190953B2 - Status: Granted - Kind: B2 - Application number: 17/541,103 - Filed: 2021-12-02 - Published: 2022-03-24 - Granted: 2025-01-07 - Earliest claimed: 2020-03-18 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Xu Li - Web page: https://patentgrep.com/patent/US12190953B2 ## CPC - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/10: Programming or data input circuits - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 16/30: Power supply circuits - G11C 16/32: Timing circuits - G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written} - G11C 16/24: Bit-line control circuits - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/35: with cell select transistors, e.g. NAND - H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor memory device includes a memory cell array, a well voltage control circuit, and a source voltage control circuit. Before writing data, first and second transistors respectively connected to a select gate line and a word line are turned on at a first timing, and a ground voltage is applied to the first transistor at a second timing and to the second transistor at a third timing. The source voltage control circuit applies a first voltage to the source line at a fourth timing that is simultaneous with or after the first timing and before the second timing, and the well voltage control circuit applies the first voltage to the well region at a fifth timing that is simultaneous with or after the first timing and before the second timing, and applies a ground voltage to the well region at a sixth timing that is after the fifth timing. ## Claims ### Claim 1 A semiconductor memory device, comprising: a conductive region having a surface extending in a first direction and a second direction intersecting the first direction; a first line connected to the conductive region; a first select gate line stacked above the conductive region in a third direction orthogonal to the first direction and the second direction; a plurality of word lines stacked above the first select gate line in the third direction; a second select gate line stacked above the word lines in the third direction; a plurality of bit lines disposed above the second select gate line in the third direction and extending in the first direction; a memory cell array including a plurality of memory strings extending in the third direction and connected between corresponding bit lines and the first line, each of the memory strings including a first select transistor having a gate to which the first select gate line is connected, memory cell transistors each having a gate to which a respective one of the word lines is connected, and a second select transistor having a gate to which the second select gate line is connected; a first voltage apply circuit configured to apply a voltage to the first line; and a row decoder configured to apply voltages to the first select gate line, the word lines, and the second select gate line, respectively, wherein before writing data to a part of the memory cell transistors having the gates connected to a selected word line among the word lines: the row decoder is controlled to: at a first timing, apply a first voltage to the first select gate line, and apply a second voltage to the selected word line, and to a non-selected word line disposed in a layer between the selected word line and the conductive region, to turn on the first select transistor and the memory cell transistors connected to the selected word line and the non-selected word line; at a second timing after the first timing, apply a third voltage lower than the first voltage to the first select gate line to turn off the first select gate transistor; at a third timing after the second timing, apply a fourth voltage higher than the third voltage to the selected word line and the non-selected word line; and at a fourth timing after the third timing, apply a fifth voltage higher than the fourth voltage to the selected word line, and the first voltage apply circuit is controlled to: at a fifth timing that is simultaneous with or after the first timing and before the second timing, apply a sixth voltage to the first line; and at a sixth timing after the second timing and before the third timing, apply a seventh voltage lower than the sixth voltage to the first line. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein a channel of each of the memory strings that are in an electrically floating state is boosted to a predetermined voltage between the first timing and the second timing. ### Claim 3 (depends on 1) The semiconductor memory device according to claim 1, wherein the fifth timing is simultaneous with the first timing. ### Claim 4 (depends on 1) The semiconductor memory device according to claim 1, wherein the fifth timing is after the first timing. ### Claim 5 (depends on 1) The semiconductor memory device according to claim 1, further comprising: a second line connected to the conductive region; and a second voltage apply circuit configured to apply a voltage to the second line, the second voltage apply circuit is controlled to at a seventh timing that is simultaneous with or after the first timing and before the second timing, apply an eighth voltage to the second line. ### Claim 6 (depends on 5) The semiconductor memory device according to claim 5, wherein the fifth timing is simultaneous with the first timing, and the seventh timing is simultaneous with the first timing. ### Claim 7 (depends on 5) The semiconductor memory device according to claim 5, wherein the fifth timing is after the first timing, and the seventh timing is simultaneous with the first timing. ### Claim 8 (depends on 5) The semiconductor memory device according to claim 5, wherein the fifth timing is after the first timing, and the seventh timing is simultaneous with the fifth timing. ### Claim 9 (depends on 5) The semiconductor memory device according to claim 5, wherein the first voltage is higher than a second voltage that is applied by the second voltage apply circuit to the second line when writing data to the selected memory cell. ### Claim 10 (depends on 5) The semiconductor memory device according to claim 5, wherein the second voltage apply circuit is further controlled to at an eighth timing that is after the second timing, apply a ninth voltage lower than the eighth voltage to the second line. ### Claim 11 (depends on 10) The semiconductor memory device according to claim 10, wherein the eighth timing is simultaneous with the sixth timing. ### Claim 12 (depends on 10) The semiconductor memory device according to claim 10, wherein the eighth timing is after the sixth timing. ### Claim 13 A method of performing a write operation on a memory cell of a semiconductor memory device that includes: a conductive region having a surface extending in a first direction and a second direction intersecting the first direction; a first line connected to the conductive region; a first select gate line stacked above the conductive region in a third direction orthogonal to the first direction and the second direction; a plurality of word lines stacked above the first select gate line in the third direction; a second select gate line stacked above the word lines in the third direction; a plurality of bit lines disposed above the second select gate line in the third direction and extending in the first direction; a memory cell array including a plurality of memory strings extending in the third direction and connected between corresponding bit lines and the first line, each of the memory strings including a first select transistor having a gate to which the first select gate line is connected, memory cell transistors each having a gate to which a respective one of the word lines is connected, and a second select transistor having a gate to which the second select gate line is connected; a first voltage apply circuit configured to apply a voltage to the first line; and a row decoder configured to apply voltages to the first select gate line, the word lines, and the second select gate line, respectively, wherein the write operation includes a precharge period and a program period after the precharge period, said method comprising: at a first timing, applying a first voltage to the first select gate line, and applying a second voltage to the selected word line, and to a non-selected word line disposed in a layer between the selected word line and the conductive region, to turn on the first select transistor and the memory cell transistors connected to the selected word line and the non-selected word line; at a second timing after the first timing, applying a third voltage lower than the first voltage to the first select gate line to turn off the first select gate transistor; at a third timing after the second timing, applying a fourth voltage higher than the third voltage to the selected word line and the non-selected word line; at a fourth timing after the third timing, applying a fifth voltage higher than the fourth voltage to the selected word line; at a fifth timing that is simultaneous with or after the first timing and before the second timing, applying a sixth voltage to the first line; and at a sixth timing after the second timing and before the third timing, applying a seventh voltage lower than the sixth voltage to the first line. ### Claim 14 (depends on 13) The method according to claim 13, wherein the fifth timing is simultaneous with the first timing. ### Claim 15 (depends on 13) The method according to claim 13, wherein the fifth timing is after the first timing. ### Claim 16 (depends on 13) The method according to claim 13, wherein the semiconductor memory device further includes: a second line connected to the conductive region; and a second voltage apply circuit configured to apply a voltage to the second line, said method further comprising: at a seventh timing that is simultaneous with or after the first timing and before the second timing, applying an eighth voltage to the second line. ### Claim 17 (depends on 16) The method according to claim 16, wherein the fifth timing is simultaneous with the first timing, and the seventh timing is simultaneous with the first timing. ### Claim 18 (depends on 16) The method according to claim 16, wherein the fifth timing is after the first timing, and the seventh timing is simultaneous with the first timing. ### Claim 19 (depends on 16) The method according to claim 16, wherein the fifth timing is after the first timing, and the seventh timing is simultaneous with the fifth timing. ### Claim 20 (depends on 16) The method according to claim 16, further comprising: at an eighth timing that is after the second timing, applying a ninth voltage lower than the eighth voltage to the second line.