# US 12,190,952 B2 · Semiconductor memory device and method of manufacturing the semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,190,952 B2 - Document ID: US12190952B2 - Status: Granted - Kind: B2 - Application number: 17/650,422 - Filed: 2022-02-09 - Published: 2023-03-23 - Granted: 2025-01-07 - Earliest claimed: 2021-09-17 - Assignees: Kioxia Corporation - Applicants: Kioxia Corporation - Inventors: Minami Tanaka; Naoyuki Iida - Web page: https://patentgrep.com/patent/US12190952B2 ## CPC - G11C 16/0483: {comprising cells having several storage transistors connected in series} - H10B 41/10: characterised by the top-view layout - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/35: with a cell select transistor, e.g. NAND - H10B 43/10: characterised by the top-view layout - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/35: with cell select transistors, e.g. NAND - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract According to one embodiment, a semiconductor memory device includes interconnect layers stacked above a substrate; a memory pillar configured to penetrate the interconnect layers; a first member and a second member; and a dividing portion provided between the first member and the second member. The dividing portion includes insulating layers. The insulating layers each include a first portion and a second portion. The first portion is provided between the first member and the second portion. The second portion is provided between the first portion and the second member. The first portion and the second portion each have an individual arc shape when viewed from a top and are in contact with each other. ## Claims ### Claim 1 A semiconductor memory device comprising: a plurality of interconnect layers stacked above a substrate and spaced apart from each other in a first direction; a memory pillar configured to penetrate the plurality of interconnect layers in the first direction; a first member and a second member each having a longitudinal direction set to a second direction intersecting the first direction when viewed from a top, the first member and the second member being arranged in the second direction and penetrating the plurality of interconnect layers in the first direction; and a dividing portion provided between the first member and the second member, wherein the dividing portion includes a plurality of insulating layers spaced apart from each other in the first direction, the plurality of insulating layers each include a first portion and a second portion, the first portion is provided between the first member and the second portion, the second portion is provided between the first portion and the second member, and the first portion and the second portion each have an individual arc shape when viewed from the top and are in contact with each other. ### Claim 2 (depends on 1) The device according to claim 1, wherein the plurality of insulating layers in the dividing portion are formed independently of the first member and the second member. ### Claim 3 (depends on 2) The device according to claim 2, wherein the first portion is in contact with one end in the longitudinal direction of the first member, and the second portion is in contact with one end in the longitudinal direction of the second member. ### Claim 4 (depends on 1) The device according to claim 1, further comprising an insulator including a metal oxide provided between at least one layer of the plurality of insulating layers and each of the first member and the second member. ### Claim 5 (depends on 1) The device according to claim 1, wherein the plurality of interconnect layers include a first area and a second area in which the memory pillar is arranged, and a third area arranged between the first area and the second area, in which the memory pillar is not arranged, and the third area includes a fourth area formed in such a manner that the plurality of interconnect layers surround an insulating area, and a fifth area having a staircase portion in which part of each of the interconnect layers is drawn out in a stepwise manner. ### Claim 6 (depends on 5) The device according to claim 5, wherein the dividing portion and the insulating area are arranged in a third direction intersecting the first direction and the second direction. ### Claim 7 (depends on 5) The device according to claim 5, wherein the dividing portion and the staircase portion are arranged in a third direction intersecting the first direction and the second direction. ### Claim 8 (depends on 5) The device according to claim 5, wherein a distance between the first member and the second member in the second direction is smaller than a distance between the insulating area and the first and second members in a third direction intersecting the first direction and the second direction. ### Claim 9 (depends on 1) The device according to claim 1, wherein the plurality of interconnect layers include a sixth area and a seventh area in which the memory pillar is not arranged, and an eighth area arranged between the sixth area and the seventh area, in which the memory pillar is arranged, the sixth area and the seventh area each have a staircase portion in which an end portion of each of the interconnect layers is drawn out in a stepwise manner, and the dividing portion and the staircase portion are arranged in a third direction intersecting the first direction and the second direction. ### Claim 10 (depends on 1) The device according to claim 1, wherein each of the interconnect layers includes a first conductor and a second conductor configured to cover a top surface and a bottom surface of the first conductor, and the second conductor is provided in such a manner as to cover a side surface of the first conductor between the first conductor and the dividing portion and not to cover the side surface of the first conductor between the first conductor and the first and second members. ### Claim 11 (depends on 1) The device according to claim 1, wherein one end in the longitudinal direction of the first member is fitted within the arc shape of the first portion of the plurality of insulating layers when viewed from the top, and one end in the longitudinal direction of the second member is fitted within the arc shape of the second portion of the plurality of insulating layers when viewed from the top. ### Claim 12 A semiconductor memory device comprising: a plurality of interconnect layers stacked above a substrate and spaced apart from each other in a first direction; a memory pillar configured to penetrate the plurality of interconnect layers in the first direction; a first member and a second member each having a longitudinal direction set to a second direction intersecting the first direction when viewed from a top, the first member and the second member being arranged in the second direction and penetrating the plurality of interconnect layers in the first direction; a dividing portion provided between the first member and the second member, the dividing portion including a plurality of insulating layers provided for the interconnect layers, respectively; and an insulator including a metal oxide provided between each of the insulating layers in the dividing portion and each of the interconnect layers. ### Claim 13 (depends on 12) The device according to claim 12, wherein each of the insulating layers and each of the interconnect layers are in contact with the insulator in a third direction intersecting the first direction and the second direction. ### Claim 14 (depends on 12) The device according to claim 12, wherein the insulator is further provided between at least one layer of the insulating layers and each of the first member and the second member. ### Claim 15 (depends on 14) The device according to claim 14, wherein each of the insulating layers, the first member, and the second member are in contact with the insulator in the second direction. ### Claim 16 (depends on 12) The device according to claim 12, wherein the insulator covers a top surface, a bottom surface, and part of a side surface of each of the interconnect layers. ### Claim 17 (depends on 16) The device according to claim 16, wherein each of the interconnect layers includes a first conductor and a second conductor configured to cover a top surface and a bottom surface of the first conductor, and the second conductor is provided in such a manner as to cover a side surface of the first conductor between the first conductor and the dividing portion and not to cover the side surface of the first conductor between the first conductor and the first and second members. ### Claim 18 (depends on 17) The device according to claim 17, wherein the insulator does not cover a side surface of each of the interconnect layers, the side surface facing the first member and the second member.