# US 12,190,949 B2 · Memory circuit and method of operating the same

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- Number: US 12,190,949 B2
- Document ID: US12190949B2
- Status: Granted
- Kind: B2
- Application number: 18/316,442
- Filed: 2023-05-12
- Published: 2023-09-07
- Granted: 2025-01-07
- Earliest claimed: 2020-07-24
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Perng-Fei Yuh; Shao-Ting Wu; Yu-Fan Lin
- Web page: https://patentgrep.com/patent/US12190949B2

## CPC

- G11C 13/0038: {Power supply circuits}
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 7/14: Dummy cell management; Sense reference voltage generators
- G11C 11/1655: {Bit-line or column circuits}
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 11/1697: {Power supply circuits}
- G11C 2013/0045: {Read using current through the cell}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory circuit includes a bias voltage generator including a first buffer configured to generate a first bias voltage based on a reference voltage and a plurality of second buffers configured to generate a plurality of second bias voltages based on the first bias voltage. The memory circuit includes a plurality of voltage clamp devices coupled to the plurality of second buffers, and each voltage clamp device is configured to apply a drive voltage to a corresponding resistance-based memory device of a plurality of resistance-based memory devices based on the corresponding second bias voltage of the plurality of second bias voltages.

## Claims

### Claim 1

A memory circuit comprising:
a bias voltage generator comprising:
a first buffer configured to generate a first bias voltage based on a reference voltage; and
a plurality of second buffers configured to generate a plurality of second bias voltages based on the first bias voltage; and
a plurality of voltage clamp devices coupled to the plurality of second buffers, wherein
each voltage clamp device of the plurality of voltage clamp devices is configured to apply a drive voltage to a corresponding resistance-based memory device of a plurality of resistance-based memory devices based on the corresponding second bias voltage of the plurality of second bias voltages.

### Claim 2 (depends on 1)

The memory circuit of claim 1, wherein
the first buffer is configured to generate a third bias voltage based on the first bias voltage, and
the bias voltage generator further comprises:
another voltage clamp device coupled to a replica path segment and configured to generate a feedback voltage based on the third bias voltage; and
an operational amplifier comprising an output terminal configured to output the first bias voltage based on the feedback voltage and the reference voltage.

### Claim 3 (depends on 2)

The memory circuit of claim 2, wherein
the bias voltage generator further comprises a capacitive device coupled between the output terminal and a power reference node.

### Claim 4 (depends on 1)

The memory circuit of claim 1, wherein
each second buffer of the plurality of second buffers comprises a first NMOS device, a first node, and a first current source coupled in series between a power source node and a power reference node,
each first NMOS device comprises a gate coupled to the first buffer and is thereby configured to receive the first bias voltage, and
each voltage clamp of the plurality of voltage clamps comprises a control terminal coupled to the first node of a corresponding second buffer of the plurality of second buffers.

### Claim 5 (depends on 4)

The memory circuit of claim 4, wherein
each first current source of a corresponding second buffer of the plurality of second buffers is configured to generate a first current having first and second current levels, and
the first current level has a magnitude higher than a magnitude of the second current level.

### Claim 6 (depends on 5)

The memory circuit of claim 5, wherein
the first buffer comprises a second NMOS device, a second node, and a second current source coupled in series between the power source node and the power reference node, and
the second current source is configured to generate a second current having a current level approximately equal to the second current level of the first current.

### Claim 7 (depends on 1)

The memory circuit of claim 1, wherein
each resistance-based memory device of the plurality of resistance-based memory devices comprises a resistive random-access memory (RRAM) device.

### Claim 8

A memory circuit comprising:
a bias voltage generator comprising:
an operational amplifier and a first buffer configured to generate a first bias voltage based on a reference voltage; and
a plurality of second buffers configured to generate a plurality of second bias voltages based on the first bias voltage; and
a plurality of voltage clamp devices coupled to the plurality of second buffers, wherein
each second buffer of the plurality of second buffers comprises a first parallel arrangement of a first current source and a second current source in series with a first switch, and
each voltage clamp device of the plurality of voltage clamp devices is configured to apply a drive voltage to a corresponding resistance-based memory device of a plurality of resistance-based memory devices based on the corresponding second bias voltage of the plurality of second bias voltages.

### Claim 9 (depends on 8)

The memory circuit of claim 8, wherein
the first buffer is configured to generate a third bias voltage based on the first bias voltage,
the bias voltage generator further comprises a voltage clamp device coupled to a replica path segment and configured to generate a feedback voltage based on the third bias voltage, and
the operational amplifier comprises an output terminal configured to output the first bias voltage based on the feedback voltage and the reference voltage.

### Claim 10 (depends on 9)

The memory circuit of claim 9, wherein, for each second buffer of the plurality of second buffers
the first parallel arrangement is coupled between a node and a power reference node,
the second buffer further comprises a second parallel arrangement of a first NMOS device and a second NMOS device in series with a second switch,
the second parallel arrangement is coupled between a power source node and the node,
each of the first and second NMOS devices comprises a gate coupled to the output terminal, and
each voltage clamp of the plurality of voltage clamps comprises a control terminal coupled to the node of a corresponding second buffer of the plurality of second buffers.

### Claim 11 (depends on 10)

The memory circuit of claim 10, wherein
the first buffer comprises a third NMOS device and a third current source coupled between the power source node and the power reference node, and
the third current source and each first current source of each second buffer of the plurality of second buffers are configured to generate respective third and first currents having a same first current level.

### Claim 12 (depends on 11)

The memory circuit of claim 11, wherein
each second current source of each second buffer of the plurality of second buffers is configured to generate a second current having a second current level higher in magnitude than the first current level.

### Claim 13 (depends on 9)

The memory circuit of claim 9, wherein, for each second buffer of the plurality of second buffers,
the first parallel arrangement is coupled between a power source node and a node,
the second buffer further comprises a second parallel arrangement of a first PMOS device and a second PMOS device in series with a second switch,
the second parallel arrangement is coupled between the node and a power reference node,
each of the first and second PMOS devices comprises a gate coupled to the output terminal, and
each voltage clamp of the plurality of voltage clamps comprises a control terminal coupled to the node of a corresponding second buffer of the plurality of second buffers.

### Claim 14 (depends on 13)

The memory circuit of claim 13, wherein
the first buffer comprises a third current source and a third PMOS device coupled between the power source node and the power reference node, and
the third current source and each first current source of each second buffer of the plurality of second buffers are configured to generate currents having a same current level.

### Claim 15 (depends on 14)

The memory circuit of claim 14, wherein
each second current source of each second buffer of the plurality of second buffers is configured to generate a second current having a second current level higher in magnitude than the first current level.

### Claim 16

A method of operating a memory circuit, the method comprising:
using a first buffer to generate a first bias voltage based on a reference voltage;
using a plurality of second buffers to generate a plurality of second bias voltages based on the first bias voltage; and
using each voltage clamp device of a plurality of voltage clamp devices to apply a drive voltage to a corresponding resistance-based memory device of a plurality of resistance-based memory devices based on a corresponding second bias voltage of the plurality of second bias voltages.

### Claim 17 (depends on 16)

The method of claim 16, wherein the using the first buffer to generate the first bias voltage comprises:
using the first buffer to generate a third bias voltage based on the first bias voltage;
using another voltage clamp device coupled to a replica path segment to generate a feedback voltage based on the third bias voltage;
receiving the reference and feedback voltages at input terminals of an operational amplifier; and
outputting the first bias voltage at an output terminal of the operational amplifier.

### Claim 18 (depends on 16)

The method of claim 16, wherein the using the plurality of second buffers to generate the plurality of second bias voltages based on the first bias voltage comprises, for each second buffer of the plurality of second buffers:
receiving the first bias voltage at a gate of first transistor coupled in series with a first current source; and
generating the corresponding second bias voltage at a node between the first transistor and the first current source.

### Claim 19 (depends on 18)

The method of claim 18, wherein the using the plurality of second buffers to generate the plurality of second bias voltages based on the first bias voltage further comprises, for each second buffer of the plurality of second buffers:
receiving the first bias voltage at a gate of second transistor coupled in series with the node and a second current source.

### Claim 20 (depends on 16)

The method of claim 16, wherein
the applying the drive voltage to the corresponding resistance-based memory device of the plurality of resistance-based memory devices comprises applying the drive voltage to a resistive random-access memory (RRAM) device.