# US 12,190,947 B2 · Imprint recovery for memory arrays

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- Number: US 12,190,947 B2
- Document ID: US12190947B2
- Status: Granted
- Kind: B2
- Application number: 17/562,598
- Filed: 2021-12-27
- Published: 2022-06-23
- Granted: 2025-01-07
- Earliest claimed: 2019-09-24
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Jonathan J. Strand; Sukneet Singh Basuta; Shashank Bangalore Lakshman; Jonathan D. Harms
- Web page: https://patentgrep.com/patent/US12190947B2

## CPC

- G11C 11/221: {using ferroelectric capacitors}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 11/2273: {Reading or sensing circuits or methods}
- G11C 11/2275: {Writing or programming circuits or methods}
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written}
- G11C 16/3431: {Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step}
- G11C 29/021: {in voltage or current generators}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/08: Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C 29/4401: {for self repair}
- G11C 29/50004: {of threshold voltage}
- G11C 29/50016: {of retention}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 29/70: {Masking faults in memories by using spares or by reconfiguring}
- G11C 2029/0409: {Online test}
- G11C 2029/0411: {Online error correction}
- G11C 2029/5004: {Voltage}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Methods, systems, and devices for imprint recovery for memory arrays are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.

## Claims

### Claim 1

A memory system, comprising:
one or more memory arrays comprising a set of memory cells; and
circuitry coupled with the one or more memory arrays and configured to cause the memory system to:
receive a command to perform an imprint recovery procedure configured to alleviate a predisposition of the set of memory cells toward storing respective first logic states over respective second logic states;
initiate the imprint recovery procedure based at least in part on receiving the command;
transmit an indication of a status of the imprint recovery procedure based at least in part on initiating the imprint recovery procedure;
receive an indication to pause the imprint recovery procedure after initiating the imprint recovery procedure;
pause the imprint recovery procedure based at least in part on receiving the indication; and
resume the imprint recovery procedure after pausing the imprint recovery procedure.

### Claim 2 (depends on 1)

The memory system of claim 1, wherein the circuitry is further configured to cause the memory system to:
detect the predisposition of the set of memory cells toward storing respective first logic states over respective second logic states; and
transmit an indication of the predisposition, wherein receiving the command is based at least in part on transmitting the indication of the predisposition.

### Claim 3 (depends on 1)

The memory system of claim 1, wherein the indication of the status of the imprint recovery procedure comprises an indication of a beginning of the imprint recovery procedure or an end of the imprint recovery procedure.

### Claim 4 (depends on 1)

The memory system of claim 1, wherein the indication of the status of the imprint recovery procedure comprises an indication of whether the imprint recovery procedure was successful.

### Claim 5 (depends on 1)

The memory system of claim 1, wherein the circuitry is further configured to cause the memory system to:
determine an error correction failure based at least in part on initiating the imprint recovery procedure, wherein the indication of the status of the imprint recovery procedure comprises an indication to replace data associated with the set of memory cells based at least in part on the error correction failure.

### Claim 6 (depends on 1)

The memory system of claim 1, wherein the indication of the status of the imprint recovery procedure comprises an indication that the one or more memory arrays is unavailable for access operations during the imprint recovery procedure.

### Claim 7 (depends on 1)

The memory system of claim 1, wherein the circuitry is further configured to cause the memory system to:
receive an indication of an available duration for performing the imprint recovery procedure; and
perform the imprint recovery procedure based at least in part on the available duration.

### Claim 8

A method, comprising:
detecting, at a host device, a condition indicative of a predisposition of memory cells of a memory device toward storing respective first logic states over respective second logic states;
transmitting, from the host device to the memory device, a command for the memory device to perform an imprint recovery procedure for alleviating the predisposition of the memory cells toward storing the respective first logic states over the respective second logic states;
receiving, at the host device, an indication of a status of the imprint recovery procedure based at least in part on transmitting the command;
transmitting, based at least in part on the indication of the status, an indication to pause the imprint recovery procedure; and
transmitting one or more access commands to the memory device based at least in part on transmitting the indication to pause the imprint recovery procedure.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
detecting a duration of storing logic states, a temperature, or an access pattern, wherein detecting the condition indicative of the predisposition toward storing the respective first logic states over the respective second logic states is based at least in part on the duration of storing logic states, the temperature, or the access pattern.

### Claim 10 (depends on 8)

The method of claim 8, further comprising:
detecting an indication of an initial startup of the memory device, wherein detecting the condition indicative of the predisposition toward storing the respective first logic states over the respective second logic states is based at least in part on the indication of the initial startup of the memory device.

### Claim 11 (depends on 8)

The method of claim 8, wherein detecting the condition indicative of the predisposition toward storing the respective first logic states over the respective second logic states comprises:
receiving an indication of the predisposition from the memory device.

### Claim 12 (depends on 8)

The method of claim 8, wherein the indication of the status of the imprint recovery procedure comprises an indication that the memory device is performing the imprint recovery procedure, the method further comprising:
suspending access operations with the memory device based at least in part on the indication that the memory device is performing the imprint recovery procedure.

### Claim 13 (depends on 8)

The method of claim 8, wherein the indication of the status of the imprint recovery procedure comprises an indication that the memory device is performing the imprint recovery procedure, the method further comprising:
performing access operations with the memory device according to a slower rate based at least in part on the indication that the memory device is performing the imprint recovery procedure.

### Claim 14 (depends on 8)

The method of claim 8, wherein the indication of the status of the imprint recovery procedure comprises an indication of a failure of the imprint recovery procedure, the method further comprising:
performing access operations with a second memory device based at least in part on the indication of a failure of the imprint recovery procedure.

### Claim 15 (depends on 8)

The method of claim 8, wherein the indication of the status of the imprint recovery procedure comprises an indication that the imprint recovery procedure was successful, the method further comprising:
transmitting one or more access commands to the memory device based at least in part on the indication that the imprint recovery procedure was successful.

### Claim 16

A method, comprising:
receiving a command to perform an imprint recovery procedure for alleviating a predisposition of a set of memory cells toward storing respective first logic states over respective second logic states;
initiating the imprint recovery procedure based at least in part on receiving the command;
transmitting an indication of a status of the imprint recovery procedure based at least in part on initiating the imprint recovery procedure;
receive an indication to pause the imprint recovery procedure after initiating the imprint recovery procedure;
pause the imprint recovery procedure based at least in part on receiving the indication; and
resume the imprint recovery procedure after pausing the imprint recovery procedure.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
detecting the predisposition of the set of memory cells toward storing respective first logic states over respective second logic states; and
transmitting an indication of the predisposition, wherein receiving the command is based at least in part on transmitting the indication of the predisposition.