# US 12,190,946 B1 · Read disturb mitigation for non-linear polar material based multi-capacitor bit-cell > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,190,946 B1 - Document ID: US12190946B1 - Status: Granted - Kind: B1 - Application number: 17/805,664 - Filed: 2022-06-06 - Granted: 2025-01-07 - Earliest claimed: 2022-06-03 - Assignees: Kepler Computing Inc. - Applicants: Kepler Computing Inc. - Inventors: Rajeev Kumar Dokania; Mustansir Yunus Mukadam; Tanay Gosavi; James David Clarkson; Neal Reynolds; Amrita Mathuriya; Sasikanth Manipatruni - Web page: https://patentgrep.com/patent/US12190946B1 ## CPC - G11C 11/2273: {Reading or sensing circuits or methods} - G11C 11/2275: {Writing or programming circuits or methods} - G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells} - G11C 11/22: using ferroelectric elements - G11C 11/221: {using ferroelectric capacitors} - G11C 11/223: {using MOS with ferroelectric gate insulating film} - G11C 11/2259: {Cell access} - G11C 11/2293: {Timing circuits or methods} - G11C 11/401: forming cells needing refreshing or charge regeneration, i.e. dynamic cells - G11C 11/419: Read-write [R-W] circuits - G11C 11/54: using elements simulating biological cells, e.g. neuron - G11C 11/5657: {using ferroelectric storage elements} - H10B 53/30: characterised by the memory core region - H10D 1/682: {having dielectrics comprising perovskite structures} - G06N 3/063: using electronic means - G06N 20/00: Machine learning - G11C 11/41: forming {static} cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger - G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS ## Abstract A disturb mitigation scheme is described for a 1TnC or multi-element ferroelectric gain bit-cell where after writing to a selected capacitor of the bit-cell, a cure phase is initiated. Between the cure phase and the write phase, there may be zero or more cycles where the selected word-line, bit-line, and plate-lines are pulled-down to ground. The cure phase may occur immediately before the write phase. In the cure phase, the word-line is asserted again just like in the write phase. In the cure phase, the voltage on bit-line is inverted compared to the voltage on the bit-line in the write phase. By programming a value in a selected capacitor to be opposite of the value written in the write phase of that selected capacitor, time accumulation of disturb is negated. This allows to substantially zero out disturb field on the unselected capacitors of the same bit-cell and/or other unselected bit-cells. ## Claims ### Claim 1 An apparatus comprising: a transistor having a gate terminal coupled to a word-line, a source terminal couple to a bit-line, and a drain terminal coupled to a storage node; a plurality of capacitors having a first terminal coupled to the storage node, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line; and one or more circuitries to perform a first read operation during a first phase on a selected capacitor of the plurality of capacitors, wherein the one or more circuitries is to perform a second read operation during a second phase, wherein the second read operation mitigates read disturb effects on unselected capacitors of the plurality of capacitors, wherein the one or more circuitries is to ramp a voltage on a plate-line coupled to the selected capacitor in a staircase fashion to a supply voltage level during the first phase, wherein the one or more circuitries is to perform a writeback operation after the second read operation, and wherein the writeback operation and the second read operation are separated by one or more cycles where the word-line, the bit-line, and the individual plate-line are pulled to ground. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the one or more circuitries is to set the voltage on the plate-line of the selected capacitor to a ground voltage level in the second phase. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the one or more circuitries is to set the bit-line to a high-impedance state during a time when the voltage on the plate-line of the selected capacitor is between the supply voltage level and the ground voltage level. ### Claim 4 (depends on 2) The apparatus of claim 2, wherein the one or more circuitries is to set voltages on plate-lines coupled to the unselected capacitors to be between the supply voltage level and the ground voltage level during the first phase and the second phase. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein a voltage on the word-line is set to the supply voltage level or a boosted supply voltage level during the first phase and the second phase. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the one or more circuitries is to perform a first write operation during a third phase on the selected capacitor of the plurality of capacitors, wherein the one or more circuitries is to perform a second write operation during a fourth phase, and wherein the second write operation mitigates write disturb effects on the unselected capacitors of the plurality of capacitors. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the first write operation or the second write operation is after the second read operation. ### Claim 8 (depends on 6) The apparatus of claim 6, wherein the first write operation and the second write operation are separated by one or more cycles where the word-line, the bit-line, and the individual plate-line are pulled to the ground. ### Claim 9 (depends on 6) The apparatus of claim 6, wherein the third phase is before the fourth phase. ### Claim 10 (depends on 6) The apparatus of claim 6, wherein the fourth phase is before the third phase. ### Claim 11 (depends on 6) The apparatus of claim 6, wherein the word-line is boosted in the third phase and the fourth phase. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein a plate-line, in the fourth phase, coupled to the selected capacitor is set to substantially half of a voltage on a power supply rail. ### Claim 13 (depends on 12) The apparatus of claim 12, wherein the plate-line of the selected capacitor is pulsed to the voltage on the power supply rail in the third phase to program the selected capacitor. ### Claim 14 (depends on 6) The apparatus of claim 6, wherein the individual plate-line coupled to the individual capacitor is set to substantially half of a voltage on a power supply rail in the fourth phase. ### Claim 15 (depends on 1) The apparatus of claim 1, wherein the individual capacitor includes non-polar linear material. ### Claim 16 An apparatus comprising: a first transistor having a first gate terminal coupled to a word-line, a first source terminal couple to a bit-line, and a first drain terminal coupled to a storage node; a second transistor coupled to the first transistor, wherein the second transistor includes a second gate terminal coupled to the storage node, a second source terminal couple to a sense line, and a second drain terminal coupled to a bias; a plurality of capacitors having a first terminal coupled to the storage node, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line; and one or more circuitries to perform a first read operation during a first phase on a selected capacitor of the plurality of capacitors, wherein the one or more circuitries is to perform a second read operation during a second phase, wherein the second read operation mitigates read disturb effects on unselected capacitors of the plurality of capacitors, wherein the one or more circuitries is to ramp a voltage on a plate-line coupled to the selected capacitor in a staircase fashion to a supply voltage level during the first phase, wherein the one or more circuitries is to set the voltage on the plate-line of the selected capacitor to a ground voltage level in the second phase, and wherein the one or more circuitries is to set the bit-line to a high-impedance state during a time when the voltage on the plate-line of the selected capacitor is between the supply voltage level and the ground voltage level. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein the one or more circuitries is to provide a first pulse on the word-line during the first phase, and to provide a second pulse on the word-line during the second phase, and wherein the first pulse and the second pulse have a voltage level substantially equal to the supply voltage level or a boosted supply voltage level. ### Claim 18 A system comprising: a processor circuitry to execute one or more instructions; a memory circuitry to store the one or more instructions; and a communication interface to allow the processor circuitry to communicate with another device, wherein the memory circuitry includes a plurality of bit-cells organized in a memory array, and wherein an individual bit-cell of the plurality of bit-cells includes: a transistor having a gate terminal coupled to a word-line, a source terminal couple to a bit-line, and a drain terminal coupled to a storage node; a plurality of capacitors having a first terminal coupled to the storage node, wherein a second terminal of an individual capacitor of the plurality of capacitors is coupled to an individual plate-line; and one or more circuitries to perform a first read operation during a first phase on a selected capacitor of the plurality of capacitors, wherein the one or more circuitries is to perform a second read operation during a second phase, wherein the second read operation mitigates read disturb effects on unselected capacitors of the plurality of capacitors, wherein the one or more circuitries is to ramp a voltage on a plate-line coupled to the selected capacitor in a staircase fashion to a supply voltage level during the first phase, wherein the one or more circuitries is to set the voltage on the plate-line of the selected capacitor to a ground voltage level in the second phase, and wherein the one or more circuitries is to set voltages on plate-lines coupled to the unselected capacitors to be between the supply voltage level and the ground voltage level during the first phase and the second phase.