# US 12,190,944 B2 · Memory device with signal edge sharpener circuitry

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- Number: US 12,190,944 B2
- Document ID: US12190944B2
- Status: Granted
- Kind: B2
- Application number: 17/234,160
- Filed: 2021-04-19
- Published: 2021-08-05
- Granted: 2025-01-07
- Earliest claimed: 2019-10-01
- Assignees: Taiwain Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Atul Katoch
- Web page: https://patentgrep.com/patent/US12190944B2

## CPC

- G11C 11/418: Address circuits
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 11/417: for memory cells of the field-effect type
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Signal edge sharpener circuitry is operably connected to the word lines in a memory array to pull up a rising edge of a signal on the word line and/or to pull down a falling edge of the signal on the word line. Pulling the signal up and/or down reduces the amount of time the word line is asserted and reduces the amount of time between precharge operations.

## Claims

### Claim 1

A method, comprising:
transmitting a clock signal to a row driver circuit and to a delay circuit:
deactivating a word line based on the clock signal received by the row driver circuit, the word line operably connected to a memory cell;
transmitting a delayed clock signal output by the delay circuit to a control terminal of signal edge sharpener circuitry operably connected to a distal end of the word line;
based on the delayed clock signal, causing, by the signal edge sharpener circuitry, a rising edge of a word line signal on the word line to be pulled up at an increased rate; and
initiating a precharge operation on a bit line in response to the rising edge of the word line signal on the word line being pulled up to a predetermined level.

### Claim 2 (depends on 1)

The method of claim 1, further comprising activating the word line when the precharge operation is completed.

### Claim 3 (depends on 1)

The method of claim 1, wherein the signal edge sharpener circuitry comprises a p-type transistor.

### Claim 4 (depends on 1)

The method of claim 1, wherein the memory cell is a static random access memory cell.

### Claim 5

A memory device, comprising:
a memory cell;
a word line operably connected to the memory cell;
a delay circuit configured to receive a clock signal and to output a delayed clock signal; and
signal edge sharpener circuitry operably connected to a distal end of the word line and to the delay circuit, the signal edge sharpener circuitry having a control terminal configured to receive the delayed clock signal from the delay circuit and responsively pull up a rising edge of a word line signal on the word line at an increased rate.

### Claim 6 (depends on 5)

The memory device of claim 5, wherein:
the signal edge sharpener circuitry comprises a p-type transistor; and
the delay circuit comprises a buffer circuit operably connected to a gate of the p-type transistor.

### Claim 7 (depends on 5)

The memory device of claim 5, further comprising a load circuit operably connected to an output of the delay circuit.

### Claim 8 (depends on 7)

The memory device of claim 7, wherein the load circuit comprises a p-type transistor, the gate of the p-type transistor operably connected to the output of the delay circuit.

### Claim 9 (depends on 5)

The memory device of claim 5, wherein:
the signal edge sharpener circuitry comprises a p-type transistor; and
the delay circuit comprises:
a select circuit operably connected to a gate of the p-type transistor;
a first plurality of buffer circuits connected in series, wherein a first output of the first plurality of buffer circuits is operably connected to a first input of the select circuit; and
a second plurality of buffer circuits connected in series, wherein a second output of the second plurality of buffer circuits is operably connected to a second input of the select circuit and the first output of the first plurality of buffer circuits is operably connected to an input of the second plurality of buffer circuits,
wherein the select circuit is operable to receive a select signal and based on the select signal, output either the first output or the second output.

### Claim 10 (depends on 5)

The memory device of claim 5, further comprising row driver circuitry operably connected to the word line.

### Claim 11 (depends on 10)

The memory device of claim 10, wherein:
the row driver circuitry comprises first row driver circuitry; and
the signal edge sharpener circuitry comprises second row driver circuitry.

### Claim 12 (depends on 5)

The memory device of claim 5, wherein the memory device is a static random access memory device.

### Claim 13

A system, comprising:
a processing device; and
a memory device operably connected to the processing device, the memory device comprising:
a memory cell;
a word line operably connected to the memory cell, wherein a proximate end of the word line is operably connected to row driver circuitry;
a delay circuit configured to receive a clock signal and output a delayed clock signal;
signal edge sharpener circuitry operably connected between a distal end of the word line and an output of the delay circuit, the signal edge sharpener circuitry having a control terminal configured to receive the delayed clock signal and responsively pull up a rising edge of a word line signal on the word line at an increased rate; and
a load circuit operably connected to the output of the delay circuit.

### Claim 14 (depends on 13)

The system of claim 13, wherein
the memory cell is included in an array of memory cells in a memory array; and
the memory device further comprises precharge circuitry operably connected between the processing device and the memory array.

### Claim 15 (depends on 13)

The system of claim 13, wherein:
the signal edge sharpener circuitry comprises a p-type transistor; and
the delay circuit comprises a buffer circuit operably connected to a gate of the p-type transistor.

### Claim 16 (depends on 13)

The system of claim 13, wherein:
the row driver circuitry comprises a NAND gate operably connected to an inverter circuit;
a first input of the NAND gate is configured to receive an address signal and a second input of the NAND gate is configured to receive a clock signal;
an output of NAND gate is operably connected to an input of the inverter; and
an output of the inverter is operably connected to the word line.

### Claim 17 (depends on 13)

The system of claim 13, wherein the load circuit comprises a p-type transistor and a gate of the p-type transistor is operably connected to the output of the delay circuit.

### Claim 18 (depends on 13)

The system of claim 13, wherein:
the signal edge sharpener circuitry comprises a p-type transistor; and
the delay circuit comprises:
a select circuit operably connected to a gate of the p-type transistor;
a first plurality of buffer circuits connected in series, wherein a first output of the first plurality of buffer circuits is operably connected to a first input of the select circuit; and
a second plurality of buffer circuits connected in series, wherein a second output of the second plurality of buffer circuits is operably connected to a second input of the select circuit and the first output of the first plurality of buffer circuits is operably connected to an input of the second plurality of buffer circuits,
wherein the select circuit is operable to receive a select signal and based on the select signal, output either the first output or the second output.

### Claim 19 (depends on 13)

The system of claim 13, further comprising one or more of:
a communication device operably connected to the processing device;
an input device operably connected to the processing device;
an output device operably connected to the processing device; or
a power supply operably connected to the processing device.

### Claim 20 (depends on 13)

The system of claim 13, wherein the memory cell is a static random access memory cell.