# US 12,190,940 B2 · Memory device and operating method thereof

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- Number: US 12,190,940 B2
- Document ID: US12190940B2
- Status: Granted
- Kind: B2
- Application number: 18/499,449
- Filed: 2023-11-01
- Published: 2024-02-29
- Granted: 2025-01-07
- Earliest claimed: 2021-02-09
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.; Tsmc Nanjing Company, Limited; Tsmc China Company Limited
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.; TSMC Nanjing Company Limited; TSMC China Company Limited
- Inventors: He-Zhou Wan; Xiu-Li Yang; Mu-Yang Ye; Yan-Bo Song
- Web page: https://patentgrep.com/patent/US12190940B2

## CPC

- G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge}
- G11C 11/417: for memory cells of the field-effect type
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders}
- G11C 11/4094: Bit-line management or control circuits
- G11C 11/413: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory device includes a first transistor, a second transistor and a third transistor. The first transistor is coupled to a first word line at a first node. The second transistor is coupled to a second word line different from the first word line at a second node. A control terminal of the first transistor is coupled to a control terminal of the second transistor. The third transistor is coupled between a ground and a third node which is coupled to each of the first node and the second node. In a layout view, each of the first transistor and the second transistor has a first length along a direction. The first transistor, the third transistor and second transistor are arranged in order along the direction. A method is also disclosed herein.

## Claims

### Claim 1

A memory device, comprising:
a first driving circuit configured to provide a first current signal from a first node to a second node according to a decoder signal;
a second driving circuit configured to provide a second current signal from the first node to a third node according to the decoder signal;
a third driving circuit configured to couple the first node to a reference voltage terminal according to the decoder signal;
a first switch configured to transmit the first current signal to the reference voltage terminal;
a second switch separated from the first switch, and configured to transmit the second current signal to the reference voltage terminal; and
a modulating circuit configured to transmit each of the first current signal and the second current signal to the reference voltage terminal when the first switch and the second switch are turned off.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the first driving circuit and the second driving circuit includes a third switch and a fourth switch, respectively,
a control terminal of the third switch is configured to receive the decoder signal, and
a control terminal of the fourth switch is configured to receive the decoder signal.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the third switch and the fourth switch are coupled to the second node and the third node, respectively.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein the first driving circuit and the third driving circuit includes a third switch and a fourth switch, respectively,
a control terminal of the third switch is configured to receive the decoder signal, and
a control terminal of the fourth switch is configured to receive the decoder signal.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein the third switch and the fourth switch are coupled to each other at the second node.

### Claim 6 (depends on 5)

The memory device of claim 5, wherein a conductive type of the third switch is different from a conductive type of the fourth switch.

### Claim 7 (depends on 1)

The memory device of claim 1, further comprising:
a first resistor coupled between the second node and the first switch; and
a second resistor coupled between the third node and the second switch,
wherein a resistance of the first resistor is substantially equal to a resistance of the second resistor.

### Claim 8 (depends on 1)

The memory device of claim 1, further comprising:
a third switch coupled in parallel with the first switch, and configured to be turned on when the first switch is turned off.

### Claim 9 (depends on 8)

The memory device of claim 8, wherein each of the first current signal and the second current signal transmitted through the third switch.

### Claim 10 (depends on 8)

The memory device of claim 8, wherein the third switch is disposed between the first switch and the second switch in a layout view.

### Claim 11 (depends on 1)

The memory device of claim 1, wherein each of the first switch and the second switch is disposed between the first driving circuit and the second driving circuit in a layout view.

### Claim 12

A memory device, comprising:
a first resistive element configured to transmit a first current signal from a first node to a second node;
a second resistive element configured to transmit a second current signal from a third node to the second node;
a first transistor configured to transmit the first current signal to the first node;
a second transistor configured to transmit the second current signal to the third node;
a third transistor coupled to the first node; and
a fourth transistor coupled between the second node and the third transistor,
wherein the third transistor has a first conductive type, and
each of the first transistor, the second transistor, and the fourth transistor has a second conductive type different from the first conductive type.

### Claim 13 (depends on 12)

The memory device of claim 12, wherein a control terminal of the first transistor is coupled to each of a control terminal of the third transistor and a control terminal of the second transistor.

### Claim 14 (depends on 12)

The memory device of claim 12, wherein the third transistor, the first transistor, the fourth transistor and the second transistor are arranged in order in a layout view.

### Claim 15 (depends on 14)

The memory device of claim 14, wherein a length of the first transistor is substantially equal to a length of the second transistor in the layout view.

### Claim 16

A method, comprising:
transmitting a first current signal to a first node by a first switch;
splitting the first current signal into a second current signal and a third current signal at the first node;
transmitting the second current signal from a second node to a reference voltage terminal according to a control signal;
transmitting the third current signal to the reference voltage terminal according to the control signal; and
coupling the second node to the reference voltage terminal by a second switch,
wherein a control terminal of the first switch is coupled to a control terminal of the second switch.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
controlling each of the first switch and the second switch by a decoder signal.

### Claim 18 (depends on 16)

The method of claim 16, wherein
transmitting the second current signal comprises transmitting the second current signal by a third switch controlled by the control signal,
transmitting the third current signal comprises transmitting the third current signal by a fourth switch controlled by the control signal, and
the third switch and the fourth switch are coupled in parallel.

### Claim 19 (depends on 18)

The method of claim 18, wherein the second switch, the third switch, the first switch and the fourth switch are arranged in order in a layout view.

### Claim 20 (depends on 19)

The method of claim 19, wherein a length of the third switch is substantially equal to a length of the fourth switch in the layout view.