# US 12,190,938 B2 · Memory driver, memory system, and operating method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,190,938 B2 - Document ID: US12190938B2 - Status: Granted - Kind: B2 - Application number: 18/150,181 - Filed: 2023-01-04 - Published: 2023-12-21 - Granted: 2025-01-07 - Earliest claimed: 2022-06-15 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Motoki Tamura; Makoto Yabuuchi - Web page: https://patentgrep.com/patent/US12190938B2 ## CPC - G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge} - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 11/4099: Dummy cell treatment; Reference voltage generators - G11C 11/413: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory driver includes a word line driver circuit, a reference circuit, and a bias circuit. The word line driver circuit is coupled to a word line and configured to selectively provide a reference voltage from a reference node to the word line according to an input signal. The reference circuit has a capacitor coupled to the reference node. The reference circuit is configured to store the reference voltage on the capacitor and lower the reference voltage from a first voltage level to a second voltage level when the reference voltage is provided by the word line driver circuit from the reference node to the word line. The bias circuit coupled to the reference node and configured to regulate the reference voltage at the reference node by the second voltage level. ## Claims ### Claim 1 A memory driver, comprising: a word line driver circuit coupled to a word line and configured to selectively provide a reference voltage from a reference node to the word line according to an input signal; a reference circuit having a capacitor coupled to the reference node, the reference circuit being configured to store the reference voltage on the capacitor and lower the reference voltage from a first voltage level to a second voltage level when the reference voltage is provided by the word line driver circuit from the reference node to the selected word line; and a bias circuit coupled to the reference node and configured to regulate the lowered reference voltage at the reference node. ### Claim 2 (depends on 1) The memory driver of claim 1, wherein after the reference voltage is lowered to the second voltage level by the reference circuit, the bias circuit is enabled to regulate the reference voltage at the reference node. ### Claim 3 (depends on 1) The memory driver of claim 1, wherein when the reference voltage is provided by the word line driver circuit from the reference node to the word line, the word line is coupled to the reference node by the word line driver. ### Claim 4 (depends on 1) The memory driver of claim 1, wherein a ratio of the second voltage level to the first voltage level is positively related to a ratio of a capacitance of the capacitor to a sum of the capacitance of the capacitor and an equivalent capacitance of the word line. ### Claim 5 (depends on 1) The memory driver of claim 1, wherein the reference circuit is configured to charge the capacitor at the reference node with an operating voltage, the reference circuit further comprises: a bias string coupled in parallel to the capacitor to limit a voltage across the capacitor at the first voltage level. ### Claim 6 (depends on 5) The memory driver of claim 5, wherein the bias string comprises a plurality of complementary metal-oxide-silicon (CMOS) transistors, each CMOS transistor being diode-connected and the plurality of CMOS transistors being coupled in series between ends of the capacitor, the first voltage level being limited by the bias string to be less than or equal to a sum of threshold voltages of the plurality of CMOS transistors. ### Claim 7 (depends on 6) The memory driver of claim 6, further comprising: a voltage trimming circuit coupled to the bias string and configured to adjust a total number of the plurality of CMOS transistors serially coupled in the bias string. ### Claim 8 (depends on 7) The memory driver of claim 7, wherein the voltage trimming circuit comprises a switch coupled in parallel with a first CMOS transistor of the plurality of CMOS transistors, so the first CMOS transistor is bypassed when the switch is closed. ### Claim 9 (depends on 1) The memory driver of claim 1, further comprising: a capacitor trimming circuit coupled in parallel with the capacitor and configured to adjust a total capacitance coupled to the reference node. ### Claim 10 (depends on 9) The memory driver of claim 9, wherein the capacitor trimming circuit comprises a switch coupled in series with a trimming capacitor, a series combination of the switch and the trimming capacitor is coupled in parallel with the capacitor, and the total capacitance coupled to the reference node is adjusted to a sum of the capacitance of the capacitor and a capacitance of the trimming capacitor when the switch is closed. ### Claim 11 A memory system, comprising: a memory array comprising a plurality of memory cells controlled by a plurality of word lines; and a memory driver, comprising: a word line driver circuit coupled to the plurality of word lines and configured to selectively provide a reference voltage from a reference node to a selected word line of the plurality of word lines according to an input signal; a reference circuit comprising a capacitor coupled to the reference node, the reference circuit being configured to store the reference voltage on the capacitor, to cause charge sharing according to a capacitance of the capacitor and an equivalent capacitance of the selected word line when the reference voltage is provided by the word line driver circuit from the reference node to the selected word line; and a bias circuit coupled to the reference node and configured to regulate the reference voltage after the reference voltage is provided from the reference node to the selected word line. ### Claim 12 (depends on 11) The memory system of claim 11, wherein the reference voltage is lowered from a first voltage level to a second voltage level through the charge sharing, a ratio of the second voltage level to the first voltage level is proportional to a ratio of a capacitance of the capacitor to a sum of the capacitance of the capacitor and the equivalent capacitance of the selected word line. ### Claim 13 (depends on 12) The memory system of claim 12, wherein the bias circuit comprises a first switch and a second switch, the first switch is coupled between the reference node and an operating voltage terminal, and the second switch is coupled between the reference node and a ground voltage terminal, both the first switch and the second switch configured to close in response to an enable signal, and the bias circuit is configured to generate the reference voltage at the second voltage level through voltage division when the enable signal is enabled. ### Claim 14 (depends on 13) The memory system of claim 13, wherein a first equivalent resistor between the reference node and the operating voltage terminal has a first resistance, and a second equivalent resistor between the reference node and the ground voltage terminal has a second resistance, and a ratio of the second resistance to a sum of the first resistance and the second resistance equals a ratio of the second voltage level to the first voltage level. ### Claim 15 (depends on 13) The memory system of claim 13, further comprising a resistance trimming circuit including a third switch and a fourth switch, the third switch and the fourth switch being coupled in series between the reference node and the ground voltage terminal, the third switch being controlled by a trimming signal and the fourth switch is controlled by the enable signal, wherein the resistance trimming circuit is configured to adjust an equivalent resistance coupled between the reference node and the ground voltage terminal when the trimming signal is enabled. ### Claim 16 (depends on 12) The memory system of claim 12, wherein the bias circuit comprises a bias string coupled between the reference node and a ground voltage terminal, the bias string comprises a plurality of complementary metal-oxide-silicon (CMOS) transistors, each CMOS transistor being diode-connected and the plurality of CMOS transistors being coupled in series between the reference node and the ground voltage terminal, the second voltage level being limited by the bias string to be less than or equal to a sum of threshold voltages of the plurality of CMOS transistors. ### Claim 17 (depends on 16) The memory system of claim 16, further comprising: a voltage trimming circuit coupled to the bias string and configured to adjust a total number of the plurality of CMOS transistors serially coupled in the bias string. ### Claim 18 (depends on 11) The memory system of claim 11, wherein the capacitor is a first capacitor, the reference circuit comprises: a first reference circuit comprising the first capacitor, the first reference circuit being enabled by a first enable signal to provide a first reference voltage to the reference node, and lower the first reference voltage when the first reference voltage is provided by the word line driver circuit from the reference node to a first selected word line of the plurality of word lines; and a second reference circuit comprising a second capacitor, the second reference circuit being enabled by a second enable signal to provide a second reference voltage to the reference node, and lower the second reference voltage when the second reference voltage is provided by the word line driver circuit from the reference node to a second selected word line of the plurality of word lines. ### Claim 19 An operating method for operating a memory array, the memory array comprising a plurality of memory cells controlled by a plurality of word lines, the operating method comprising: storing a reference voltage on a capacitor and coupling the capacitor to a reference node to provide the reference voltage to the reference node; selectively providing the reference voltage to a selected word line of the plurality of word lines; lowering the reference voltage from a first voltage level to a second voltage level by voltage sharing between the capacitor and an equivalent capacitance of the selected word line when the reference voltage is provided from the reference node to the selected word line of the plurality of word lines; and regulating the lowered reference voltage at the reference node. ### Claim 20 (depends on 19) The operating method of claim 19, wherein a ratio of the second voltage level to the first voltage level is positively related to a ratio of a capacitance of the capacitor to a sum of the capacitance of the capacitor and an equivalent capacitance of the selected word line.