# US 12,190,935 B2 · Memory and operation method thereof

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- Number: US 12,190,935 B2
- Document ID: US12190935B2
- Status: Granted
- Kind: B2
- Application number: 17/980,141
- Filed: 2022-11-03
- Published: 2023-11-30
- Granted: 2025-01-07
- Earliest claimed: 2022-05-24
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Sang Woo Yoon
- Web page: https://patentgrep.com/patent/US12190935B2

## CPC

- G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0653: {Monitoring storage devices or systems}
- G06F 3/0673: {Single storage device}
- G11C 11/40603: {Arbitration, priority and concurrent access to memory cells for read/write or refresh operations}
- G11C 11/40611: {External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh}
- G11C 11/4078: Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells (protection of memory contents during checking or testing G11C29/52)
- G11C 11/408: Address circuits
- G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders}
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/4094: Bit-line management or control circuits
- G11C 29/1201: {comprising I/O circuitry}
- G11C 2029/1204: {Bit line control}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An operation method of a memory may include receiving an active command and an active address; determining whether a row corresponding to the active address and a row corresponding to a target row address are able to be substantially simultaneously activated; activating the row corresponding to the active address; and activating the row corresponding to the target row address in response to determining that the row corresponding to the active address and the row corresponding to the target row address are able to be substantially simultaneously activated.

## Claims

### Claim 1

An operation method of a memory, the operation method comprising:
receiving an active command and an active address;
determining whether a row corresponding to the active address and a row corresponding to a target row address share a bit line sense amplifier;
activating the row corresponding to the active address; and
activating the row corresponding to the target row address when the row corresponding to the active address and the row corresponding to the target row address are determined to share the bit line sense amplifier.

### Claim 2 (depends on 1)

The operation method of claim 1, further comprising, before the determining whether the row corresponding to the active address and the row corresponding to the target row address share the bit line sense amplifier, determining whether the target row address is generated.

### Claim 3 (depends on 2)

The operation method of claim 2, wherein the determining whether the target row address is generated includes:
counting a number of times by which the active command is applied; and
determining whether a result of the counting matches a predetermined value.

### Claim 4 (depends on 1)

The operation method of claim 1, further comprising:
receiving a read command and a read address;
reading, after the activating of the rows, data from memory cells of columns corresponding to the read address in the row corresponding to the active address; and
transmitting the data to a memory controller.

### Claim 5 (depends on 1)

The operation method of claim 1, further comprising:
receiving a write command, a write address, and write data; and
writing, after the activating of the rows, the write data to memory cells of columns corresponding to the write address in the row corresponding to the active address.

### Claim 6 (depends on 1)

The operation method of claim 1, further comprising:
receiving a precharge command; and
precharging, after the activating of the rows, the row corresponding to the active address and the row corresponding to the target row address, in response to the precharge command.

### Claim 7

A memory comprising:
a target row refresh operation control circuit configured to determine whether to perform a target row refresh operation during an active operation by determining whether a row corresponding to an active address and a target row corresponding to a target row address share a bit line sense amplifier;
a target row collection circuit configured to collect the target row address; and
a memory core including memory cells arranged in a plurality of rows and a plurality of columns and configured to activate the row corresponding to the active address and the target row corresponding to the target row address when it is determined to perform the target row refresh operation during the active operation.

### Claim 8 (depends on 7)

The memory of claim 7, wherein the target row refresh operation control circuit determines whether to perform the target row refresh operation during the active operation by further determining whether the target row address is collected by the target row collection circuit.

### Claim 9 (depends on 8)

The memory of claim 8, wherein the target row refresh operation control circuit determines, whenever an active command is applied a predetermined number of times, whether the target row address is collected by the target row collection circuit.

### Claim 10 (depends on 7)

The memory of claim 7, wherein, in a state in which the rows corresponding to the active address and the target row address are activated, the memory core is further configured to read, in response to a read command and a read address, data from memory cells selected by the read address in the row corresponding to the active address.

### Claim 11 (depends on 7)

The memory of claim 7, wherein, in a state in which the rows corresponding to the active address and the target row address are activated, the memory core is further configured to write, in response to a write command and a write address, write data to memory cells selected by the write address in the row corresponding to the active address.

### Claim 12 (depends on 7)

The memory of claim 7, wherein the memory core activates the rows by activating the row corresponding to the active address and then the row corresponding to the target row address.