# US 12,190,931 B2 · Semiconductor memory devices and methods of manufacturing thereof

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- Number: US 12,190,931 B2
- Document ID: US12190931B2
- Status: Granted
- Kind: B2
- Application number: 18/336,386
- Filed: 2023-06-16
- Published: 2023-10-12
- Granted: 2025-01-07
- Earliest claimed: 2021-03-12
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Peng-Chun Liou; Zhiqiang Wu; Chung-Wei Wu; Yi-Ching Liu; Yih Wang
- Web page: https://patentgrep.com/patent/US12190931B2

## CPC

- G11C 11/223: {using MOS with ferroelectric gate insulating film}
- G11C 11/2257: {Word-line or row circuits}
- G11C 11/2255: {Bit-line or column circuits}
- G11C 11/2297: {Power supply circuits}
- H10B 51/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures are configured to be applied with respective different voltages in accordance with the varying width of the first and second conductive structures.

## Claims

### Claim 1

A semiconductor device, comprising:
a first conductive structure extending along a vertical direction;
a second conductive structure extending along the vertical direction, wherein the second conductive structure is spaced apart from the first conductive structure along a lateral direction; and
a plurality of third conductive structures each extending along the lateral direction, wherein the plurality of third conductive structures are separated from one another along the vertical direction and disposed across the first and second conductive structures;
wherein the first and second conductive structures respectively are first and second bit lines that each have a width extending in the lateral direction and varying along the vertical direction.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a semiconductor channel extending along the vertical direction and in contact with the first and second conductive structures; and
a memory film extending along the vertical direction and interposed between the semiconductor channel and the plurality of third conductive structures.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the memory film includes a ferroelectric layer.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein the first conductive structure and the second conductive structure are in contact with end portions of a sidewall of the semiconductor channel, respectively.

### Claim 5 (depends on 2)

The semiconductor device of claim 2, wherein each of the plurality of third conductive structures, the first conductive structure, the second conductive structure, a portion of the semiconductor channel, and a portion of the memory film collectively operate as one of a plurality of memory cells of a memory string.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the plurality of memory cells conduct a current with a constant level.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the varying width increases with an increasing height of the first and second conductive structures.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein voltages applied to the plurality of third conductive structures decrease from a bottommost one of the plurality of third conductive structures to a topmost one of the plurality of third conductive structures.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the varying width having a first portion increases and a second portion decreases, with an increasing height of the first and second conductive structures.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein voltages applied to the plurality of third conductive structures decrease from a bottommost one of the plurality of third conductive structures to a middle one of the plurality of third conductive structures and increase from the middle third conductive structure to a topmost one of the plurality of third conductive structures.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the varying width having a first portion decreases and a second portion increases, with an increasing height of the first and second conductive structures.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein voltages applied to the plurality of third conductive structures increase from a bottommost one of the plurality of third conductive structures to a middle one of the plurality of third conductive structures and decrease from the middle third conductive structure to a topmost one of the plurality of third conductive structures.

### Claim 13

A memory device, comprising:
a first bit/source line extending along a vertical direction;
a second bit/source line extending along the vertical direction; and
a plurality of first word lines each extending along a first lateral direction;
wherein the first and second bit/source lines each have a width extending along the first lateral direction, the width varying in accordance with a varying height of the first and second bit/source lines.

### Claim 14 (depends on 13)

The memory device of claim 13, further comprising:
a first memory film extending along the vertical direction, the first memory film in contact with the plurality of first word lines; and
a first semiconductor channel extending along the vertical direction, the first semiconductor channel in contact with the first and second bit/source lines and with the first memory film on respective sides;
wherein the first bit/source line, the second bit/source line, one of the first word lines, a portion of the first semiconductor channel, and a portion of the first memory film collectively operate as one of a plurality of first memory cells.

### Claim 15 (depends on 14)

The memory device of claim 14, further comprising:
a plurality of second word line extending along the first lateral direction, the second word lines disposed opposite the first and second bit/source lines from the first word lines along a second lateral direction perpendicular to the first lateral direction;
a second memory film extending along the vertical direction, the second memory film in contact with the plurality of second word lines; and
a second semiconductor channel extending along the vertical direction, the second semiconductor channel in contact with the first and second bit/source lines and with the second memory film on respective sides.

### Claim 16 (depends on 15)

The memory device of claim 15, wherein the first bit/source line, the second bit/source line, one of the second word lines, a portion of the second semiconductor channel, and a portion of the second memory film collectively operate as one of a plurality of second memory cells.

### Claim 17 (depends on 15)

The memory device of claim 15, wherein the plurality of first word lines are separated from one another along the vertical direction, and the plurality of second word lines are separated from one another along the vertical direction.

### Claim 18 (depends on 15)

The memory device of claim 15, wherein each of the first memory film and the second memory film includes a ferroelectric layer.

### Claim 19

A memory device, comprising:
a memory array comprising a plurality of memory strings, each of the plurality of memory strings comprising a plurality of memory cells arranged along a vertical direction;
wherein each of the plurality of memory strings comprises:
a first bit/source line extending along the vertical direction;
a second bit/source line extending along the vertical direction;
a plurality of word lines spaced from one another along the vertical direction and each extending along a lateral direction;
wherein the first and second bit/source lines each have a width extending along the first lateral direction, and the width varies in accordance with a varying height of the first and second bit/source lines.

### Claim 20 (depends on 19)

The memory device of claim 19, wherein each of the plurality of memory strings further comprises:
a memory film extending along the vertical direction, wherein the memory film is in contact with the plurality of word lines; and
a semiconductor channel extending along the vertical direction, wherein the semiconductor channel is in contact with the first and second bit/source lines and with the memory film on opposite sides along a second lateral direction perpendicular to the first lateral direction.