# US 12,190,929 B2 · Memory array, memory cell, and data read and write method thereof

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- Number: US 12,190,929 B2
- Document ID: US12190929B2
- Status: Granted
- Kind: B2
- Application number: 18/053,898
- Filed: 2022-11-09
- Published: 2023-06-22
- Granted: 2025-01-07
- Earliest claimed: 2021-12-20
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Yulei Wu; Xiaoguang Wang
- Web page: https://patentgrep.com/patent/US12190929B2

## CPC

- G11C 11/1659: {Cell access}
- G11C 11/1675: {Writing or programming circuits or methods}
- G11C 11/1655: {Bit-line or column circuits}
- G11C 11/1657: {Word-line or row circuits}
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 11/1693: {Timing circuits or methods}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present disclosure provides a memory array, a memory cell, and a data read and write method thereof. Two storage nodes are provided in each memory cell of a memory array of a magnetic random access memory (MRAM), such that when one storage node in the memory cell fails, the other storage node in the memory cell can be used to write and read data.

## Claims

### Claim 1

A memory cell, comprising:
a first storage node, separately connected to a first terminal of a transistor and a first bit line;
a second storage node, separately connected to the first terminal of the transistor and a second bit line;
the transistor, provided with a second terminal connected to a source line and a third terminal connected to a word line; and
a switch structure, configured to control conduction between a first terminal and a third terminal thereof, or to control the conduction between a second terminal and the third terminal thereof.

### Claim 2 (depends on 1)

The memory cell according to claim 1, wherein
the first storage node and the second storage node are arranged in parallel.

### Claim 3 (depends on 1)

The memory cell according to claim 1, wherein
the first storage node comprises a first magnetic tunnel junction provided with a first terminal connected to the first bit line and a second terminal connected to the first terminal of the transistor, and having a first magnetic characteristic;
the second storage node comprises a second magnetic tunnel junction provided with a first terminal connected to the second bit line and a second terminal connected to the first terminal of the transistor, and having a second magnetic characteristic; and
the first magnetic characteristic is different from the second magnetic characteristic.

### Claim 4 (depends on 3)

The memory cell according to claim 3, wherein
the first magnetic tunnel junction and/or the second magnetic tunnel junction each comprise a bottom electrode layer, a free layer, a tunnel barrier layer, a reference layer, and a top electrode layer.

### Claim 5 (depends on 1)

A memory array, comprising:
m source lines, m word lines, n first bit lines, n second bit lines, and memory cells of m rows and n columns, wherein the memory cells are the memory cell according to claim 1, and m and n are positive integers; and
each of the memory cells located on a same row are connected to a same word line and a same source line, the first storage node of each of the memory cells located on a same column is connected to a same first bit line, and the second storage node of each of the memory cells located on a same column is connected to a same second bit line.

### Claim 6 (depends on 5)

The memory array according to claim 5, wherein
the first bit lines and the second bit lines are arranged in parallel.

### Claim 7 (depends on 1)

A data read and write method of a memory cell, comprising:
performing data writing or data reading on the memory cell according to claim 1.

### Claim 8 (depends on 7)

The method according to claim 7, wherein
the performing data writing or data reading on the memory cell comprises: controlling the first storage node to perform the data writing or the data reading through the first bit line, the source line, and the word line.

### Claim 9 (depends on 7)

The method according to claim 7, wherein
the performing data writing or data reading on the memory cell comprises: controlling the second storage node to perform the data writing or the data reading through the second bit line, the source line, and the word line.

### Claim 10 (depends on 8)

The method according to claim 8, wherein
the performing data writing or data reading on the memory cell comprises:
determining whether the first storage node fails;
when yes, performing the data writing or the data reading on the second storage node; and
when not, performing the data writing or the data reading on the first storage node.

### Claim 11 (depends on 10)

The method according to claim 10, wherein
the determining whether the first storage node fails comprises: determining, according to a read and write state identifier of the first storage node, whether the first storage node fails.

### Claim 12 (depends on 8)

The method according to claim 8, wherein
the performing data writing or data reading on the memory cell comprises:
determining a first magnetic characteristic of the first storage node, a second magnetic characteristic of the second storage node, and a target magnetic characteristic required when the data writing or the data reading is performed on the memory cell;
performing the data writing or the data reading on the first storage node when the target magnetic characteristic is the same as the first magnetic characteristic; and
performing the data writing or the data reading on the second storage node when the target magnetic characteristic is the same as the second magnetic characteristic.

### Claim 13 (depends on 1)

A data read and write device of a memory cell, comprising:
a write module, configured to perform data writing on the memory cell according to claim 1; and
a read module, configured to perform data reading on the memory cell according to claim 1.

### Claim 14 (depends on 13)

The device according to claim 13, wherein
the write module is configured to control the first storage node to perform the data writing through the first bit line, the source line, and the word line, and to control the second storage node to perform the data writing through the second bit line, the source line, and the word line; and
the read module is configured to control the first storage node to perform the data reading through the first bit line, the source line, and the word line, and to control the second storage node to perform the data reading through the second bit line, the source line, and the word line.

### Claim 15

A data read and write method of a memory cell, comprising:
providing the memory cell comprising:
a first storage node, separately connected to a first terminal of a transistor and a first bit line;
a second storage node, separately connected to the first terminal of the transistor and a second bit line;
the transistor, provided with a second terminal connected to a source line and a third terminal connected to a word line; and
a switch structure, configured to control conduction between a first terminal and a third terminal thereof, or to control the conduction between a second terminal and the third terminal thereof;
performing data writing or data reading on the memory cell comprising:
determining whether the first storage node fails, wherein
when it is determined that the first storage node fails, performing the data writing or the data reading on the second storage node; and
when it is determined that the first storage node does not fail, performing the data writing or the data reading on the first storage node.

### Claim 16 (depends on 15)

The method according to claim 15, wherein
the performing data writing or data reading on the memory cell comprises: controlling the first storage node to perform the data writing or the data reading through the first bit line, the source line, and the word line.

### Claim 17 (depends on 15)

The method according to claim 15, wherein
the performing data writing or data reading on the memory cell comprises: controlling the second storage node to perform the data writing or the data reading through the second bit line, the source line, and the word line.

### Claim 18 (depends on 15)

The method according to claim 15, wherein
the determining whether the first storage node fails comprises: determining, according to a read and write state identifier of the first storage node, whether the first storage node fails.

### Claim 19 (depends on 15)

The method according to claim 15, wherein
the performing data writing or data reading on the memory cell comprises:
determining a first magnetic characteristic of the first storage node, a second magnetic characteristic of the second storage node, and a target magnetic characteristic required when the data writing or the data reading is performed on the memory cell;
performing the data writing or the data reading on the first storage node when the target magnetic characteristic is the same as the first magnetic characteristic; and
performing the data writing or the data reading on the second storage node when the target magnetic characteristic is the same as the second magnetic characteristic.

### Claim 20

A data read and write method of a memory cell, comprising:
providing the memory cell comprising:
a first storage node, separately connected to a first terminal of a transistor and a first bit line;
a second storage node, separately connected to the first terminal of the transistor and a second bit line;
the transistor, provided with a second terminal connected to a source line and a third terminal connected to a word line; and
a switch structure, configured to control conduction between a first terminal and a third terminal thereof, or to control the conduction between a second terminal and the third terminal thereof;
performing data writing or data reading on the memory cell comprising:
determining whether the first storage node fails, wherein
when it is determined that the first storage node fails, performing the data writing or the data reading on the second storage node; and
when it is determined that the first storage node does not fail, performing the data writing or the data reading on the first storage node.