# US 12,190,927 B2 · Memory device with a bias circuit

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- Number: US 12,190,927 B2
- Document ID: US12190927B2
- Status: Granted
- Kind: B2
- Application number: 17/407,875
- Filed: 2021-08-20
- Published: 2023-02-23
- Granted: 2025-01-07
- Earliest claimed: 2021-08-20
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Meng-Sheng Chang; Chia-En Huang; Gu-Huan Li
- Web page: https://patentgrep.com/patent/US12190927B2

## CPC

- G11C 11/1657: {Word-line or row circuits}
- G11C 11/1655: {Bit-line or column circuits}
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 11/1675: {Writing or programming circuits or methods}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method for operating a memory device is provided. A first address is decoded to select a bit line of a memory device. A second address is decoded to select a word line of the memory device. A word line voltage is applied to the selected word line. A bit line voltage is applied to the selected bit line. A first bias voltage is applied to each of a plurality of unselected word lines connected to a plurality of memory cells connected to the selected bit line san a memory cell connected to both the selected bit line and the selected word line.

## Claims

### Claim 1

A method for operating a memory device, the method comprising:
decoding a first address to select a bit line of a memory device;
decoding a second address to select a word line of the memory device;
applying a word line voltage to the selected word line;
applying a bit line voltage to the selected bit line;
applying a first bias voltage to each of a plurality of unselected word lines connected to a plurality of memory cells connected to the selected bit line except a memory cell connected to both the selected bit line and the selected word line, the first bias voltage being different than the word line voltage applied to the selected word line, wherein applying the first bias voltage comprises applying the first bias voltage that is less than 0 volt; and
applying a second bias voltage to a gate of a reference memory cell transistor of a reference circuit, wherein the second bias voltage is greater than a supply voltage of the memory device.

### Claim 2 (depends on 1)

The method of claim 1, further comprising comparing a reference current generated by a reference circuit and a read current flowing through the memory device.

### Claim 3 (depends on 2)

The method of claim 2, further comprising providing a first bit value as an output when the reference current is greater than the read current.

### Claim 4 (depends on 2)

The method of claim 2, further comprising providing a second bit value as an output when the reference current is less than the read current.

### Claim 5 (depends on 1)

The method of claim 1, wherein the memory device comprises a memory cell array comprising:
multiple memory cells arranged in a matrix of rows and columns,
a plurality of bit lines, each of the plurality of bit lines connected to a first plurality of memory cells in a row of memory cell array; and
a plurality of word lines, each of the plurality of word lines connected to a second plurality of memory cells in a column of memory cell array.

### Claim 6 (depends on 1)

The method of claim 1, wherein the memory device comprises a memory cell array comprising a plurality of Magnetic Random Access Memory (MRAM) cells.

### Claim 7

A method of performing a read operation in a memory device, the method comprising:
applying a word line voltage to a selected word line of a memory device;
applying a bit line voltage to a selected bit line of the memory device;
applying a first bias voltage to each of a plurality of unselected word lines connected a plurality of memory cells connected to the selected bit line except a memory cell connected to both the selected word line and the selected bit line, the first bias voltage being different than the word line voltage applied to the selected word line, wherein applying the first bias voltage comprises applying the first bias voltage that is less than 0 volt;
applying a second bias voltage to a gate of a reference memory cell transistor of a reference circuit, wherein the second bias voltage is greater than a supply voltage of the memory device; and
comparing a reference current generated by the reference circuit and a read current flowing through the memory device.

### Claim 8 (depends on 7)

The method of claim 7, further comprising providing a first bit value as an output when the reference current is less than the read current.

### Claim 9 (depends on 7)

The method of claim 7, further comprising providing a second bit value as an output when the reference current is greater than the read current.

### Claim 10 (depends on 7)

The method of claim 7, further comprising disabling a write path before performing a read operation on the memory device.

### Claim 11 (depends on 7)

The method of claim 7, further comprising:
disabling a write path before performing a read operation on the memory device; and
enabling a write path before performing the read operation on the memory device.

### Claim 12 (depends on 7)

The method of claim 7, further comprising performing a write operation in the memory device, wherein performing the write operation in the memory device further comprises:
enabling a write path before performing the write operation on the memory device; and
disabling the write path before performing the read operation on the memory device.

### Claim 13

A memory device comprising:
a word line decoder connected to a memory cell array, wherein the word line decoder selects a word line of the memory cell array;
a bit line decoder connected to the memory cell array, wherein the bit line decoder selects a bit line of the memory cell array;
a reference circuit to generate a reference current;
a sense amplifier connected to the reference circuit and the memory cell array, wherein the sense amplifier compares a read current flowing to the memory cell array and the reference current; and
a bias circuit configured to:
apply a first bias voltage to a to each of a plurality of unselected word lines connected to a plurality of memory cells connected to the selected bit line except a memory cell connected to both the selected word line and the selected bit line, the first bias voltage being different than a word line voltage applied to the selected word line, wherein applying the first bias voltage comprises applying the first bias voltage that is less than 0 volt, and
apply a second bias voltage to a gate of a reference memory cell transistor of the reference circuit, wherein the second bias voltage is greater than a supply voltage of the memory device.

### Claim 14 (depends on 13)

The memory device of claim 13, wherein the first bias voltage is −0.3 volt.

### Claim 15 (depends on 13)

The memory device of claim 13, wherein the memory cell array comprises:
multiple memory cells arranged in a matrix of rows and columns,
a plurality of bit lines, each of the plurality of bit lines connected to a first plurality of memory cells in a row of memory cell array; and
a plurality of word lines, each of the plurality of word lines connected to a second plurality of memory cells in a column of memory cell array.

### Claim 16 (depends on 13)

The memory device of claim 13, wherein the memory cell array comprises a plurality of Magnetic Random Access Memory (MRAM) cells.

### Claim 17 (depends on 13)

The memory device of claim 13, wherein the second bias voltage is greater than 0.75 volt.

### Claim 18 (depends on 13)

The memory device of claim 13, wherein the bias circuit is further configured to:
apply a third bias voltage to another selected word line for a write operation, wherein the third bias voltage is greater than the second bias voltage.

### Claim 19 (depends on 13)

The memory device of claim 13, wherein the bias circuit comprises:
a negative voltage generator circuit to generate the first bias voltage; and
a charge pump to generate the second bias voltage.

### Claim 20 (depends on 13)

The memory device of claim 13, wherein the first bias voltage and the second bias voltage are applied during a read operation.