# US 12,190,850 B2 · Display driving device and method of driving display system

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- Number: US 12,190,850 B2
- Document ID: US12190850B2
- Status: Granted
- Kind: B2
- Application number: 18/073,092
- Filed: 2022-12-01
- Published: 2023-06-29
- Granted: 2025-01-07
- Earliest claimed: 2021-12-27
- Assignees: Lx Semicon Co., Ltd.
- Applicants: Lx Semicon Co., Ltd.
- Inventors: Byeong Ho Jeong; Sung Ha Kim
- Web page: https://patentgrep.com/patent/US12190850B2

## CPC

- G09G 3/2003: {Display of colours (specific for liquid crystal displays G09G3/3607)}
- G09G 5/18: Timing circuits for raster scan displays (specially adapted for television H04N {; synchronisation between the display unit and other display units, videodisc player G09G5/12})
- G09G 5/395: Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen (G09G5/399 takes precedence)
- G09G 3/3275: Details of drivers for data electrodes
- G09G 3/3685: {Details of drivers for data electrodes}
- G09G 2300/0452: Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
- G09G 2310/027: Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
- G09G 2310/0294: Details of sampling or holding circuits arranged for use in a driver for data electrodes
- G09G 2310/0297: Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2320/0242: Compensation of deficiencies in the appearance of colours
- G09G 2330/06: Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A display driving device according to the present disclosure capable of changing image data at a different time for each color when the image data is changed includes: a first array composed of sampling latches configured to latch n-bit image data for each channel; a second array composed of holding latches configured to latch the image data latched in the sampling latches at a latch timing determined for each latch group; a signal generation circuit configured to generate a latch enable signal which causes the holding latches to perform a latch operation at the latch timing determined for each latch group; and a third array including level shifters configured to shift a voltage level of the image data output from the holding latches.

## Claims

### Claim 1

A display driving device comprising:
a first array composed of a plurality of sampling latches configured to latch n-bit image data for each channel;
a second array composed of a plurality of holding latches configured to latch the image data latched in the sampling latches at a latch timing determined for each of a plurality of latch groups;
a signal generating circuit configured to generate a plurality of latch enable signal corresponding to the plurality of latch groups and apply each of the plurality of latch enable signals to the holding latches correspond of the plurality of latch groups so that holding latches included in different latch groups operate at different timings to latch image data latched in the sampling latches as different latch timing; and
a third array composed of level shifters configured to shift a voltage level of the image data output from the holding latches,
wherein each of the latch groups is composed of holding latches.

### Claim 2 (depends on 1)

The display driving device of claim 1, wherein:
the latch enable signal for each latch group transitions from a low level to a high level when a first number of clock pulses is counted from a rising edge of a horizontal synchronization signal (Hsync) which indicates a start of one horizontal line, and transitions from the high level to the low level when a second number of clock pulses is counted from the rising edge; and
the first number of clock pulses and the second number of the clock pulses are set differently for each latch group.

### Claim 3 (depends on 1)

The display driving device of claim 1, wherein:
a unit pixel included in a display panel is composed of a red sub-pixel, a first green sub-pixel, a blue sub-pixel, and a second green sub-pixel; and
the plurality of latch groups include a first latch group composed of holding latches configured to latch image data of the read sub-pixel, a second latch group composed of holding latches configured to latch image data of the first green sub-pixel, a third latch group composed of holding latches configured to latch image data of the blue sub-pixel, and a fourth latch group composed of holding latches configured to latch image data of the second green sub-pixel.

### Claim 4 (depends on 3)

The display driving device of claim 3, wherein the holding latches included in the second and fourth latch groups perform a latch operation before the holding latches included in the first and third latch groups.

### Claim 5 (depends on 1)

The display driving device of claim 1, further comprising a register in which different latch timings are recorded for each latch group,
wherein the signal operation circuit generates the latch enable signal based on the latch timings for each latch group recorded in the register.

### Claim 6 (depends on 1)

The display driving device of claim 1, wherein the holding latches latch the image data output from the sampling latches during a section in which the latch enable signal is at a high level.

### Claim 7 (depends on 6)

The display driving device of claim 6, wherein the signal generation circuit generates the latch enable signal so that high level sections of the latch enable signals for each latch group do not overlap each other.

### Claim 8

A display driving device comprising:
a first array composed of sampling latches configured to latch n-bit image data for each channel;
a second array composed of holding latches configured to latch the image data latched in the sampling latches at a latch timing determined for each cell group;
a signal generation circuit configured to generate a latch enable signal which causes the holding latches to perform a latch operation at the latch timing determined for each cell group; and
a third array composed of level shifters configured to shift a voltage level of the image data output from the holding latches,
wherein the cell group is composed of latch cells at the same position among latch cells constituting each holding latch; and
wherein the signal generation circuit generates the latch enable signal for each cell group so that bits of the image data are sequentially latched in an order from a first cell group composed of first latch cells in which significant bits (MSBs) of the image data for each channel are latched in the holding latches to an nth cell group composed of nth latch cells in which least significant bits (LSBs) of the image data for each channel are latched in the holding latches.

### Claim 9 (depends on 8)

The display driving device of claim 8, wherein:
the latch enable signal for each cell group transitions from a low level to a high level when a first number of clock pulses is counted from a rising edge of a horizontal synchronization signal (Hsync) which indicates a start of one horizontal line, and transitions from the high level to the low level when a second number of clock pulses is counted from the rising edge; and
the first number of clock pulses and the second number of clock pulses are set differently for each cell group.

### Claim 10 (depends on 8)

The display driving device of claim 8, wherein the holding latches latch the image data output from the sampling latches during a section in which the latch enable signal is at a high level, and
wherein the signal generation circuit generates the latch enable signal so that high level sections of the latch enable signals for each cell group do not overlap each other.

### Claim 11 (depends on 8)

The display driving device of claim 8, further comprising a register in which different latch timings are recorded for each cell group,
wherein the signal generation circuit generates the latch enable signal based on the latch timings for each cell group recorded in the register.

### Claim 12

A method of driving a display system, comprising:
latching, by sampling latches, n-bit image data generated for each channel;
generating a latch enable signal which causes holding latches to perform a latch operation at different latch timings determined for each latch group or each cell group;
latching, by the holding latches, the image data latched in the sampling latches at the different latch timings according to the latch enable signal generated for each latch group or each cell group; and
shifting a voltage level of the image data latched in the holding latches,
wherein the latch group is composed of holding latches, and
wherein, in the generating of the latch enable signal, the latch enable signal is generated for each cell group so that bits of the image data are sequentially latched in an order from a first cell group composed of first latch cells in which most significant bits (MSBs) of the image data for each channel are latched in the holding latches to an nth cell group composed of nth latch cells in which least significant bits (LSBs) of the image data for each channel are latched in the holding latches.

### Claim 13 (depends on 12)

The method of claim 12, wherein a unit pixel included in a display panel is composed of a red sub-pixel, a first green sub-pixel, a blue sub-pixel, and a second green sub-pixel, and
wherein the latch group includes a first latch group composed of holding latches configured to latch image data of the red sub-pixel, a second latch group composed of holding latches configured to latch image data of the first green sub-pixel, a third latch group composed of holding latches configured to latch image data of the blue sub-pixel, and a fourth latch group composed of holding latches configured to latch image data of the second green sub-pixel.

### Claim 14 (depends on 13)

The method of claim 13, wherein, in the generating of the latch enable signal, the latch enable signal is generated so that the holding latches included in the second and fourth latch groups perform a latch operation before the holding latches included in the first and third latch groups.

### Claim 15 (depends on 12)

The method of claim 12, wherein the cell group is composed of latch cells at the same position among latch cells constituting each holding latch.

### Claim 16 (depends on 12)

The method of claim 12, wherein the holding latches latch the image data output from the sampling latches during a section in which the latch enable signal is at a high level.

### Claim 17 (depends on 12)

The method of claim 12, wherein, in the generating of the latch enable signal, the latch enable signal for each latch group or each cell group transitions from a low level to a high level when a first number of clock pulses is counted from a rising edge of a horizontal synchronization signal (Hsync) which indicates a start of one horizontal line, and transitions from the high level to the low level when a second number of clock pulses is counted from the rising edge; and
the first number of clock pulses and the second number of clock pulses are set differently for each latch group or each cell group.