# US 12,190,824 B2 · Transmission gate circuit, inverter circuit and gate driving circuit including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,190,824 B2 - Document ID: US12190824B2 - Status: Granted - Kind: B2 - Application number: 18/205,901 - Filed: 2023-06-05 - Published: 2024-02-15 - Granted: 2025-01-07 - Earliest claimed: 2022-08-12 - Assignees: Samsung Display Co., Ltd.; Konkuk University Industrial Cooperation Corp. - Applicants: Samsung Display Co., Ltd.; Konkuk University Industrial Cooperation Corp - Inventors: Kyungho Kim; Keechan Park; Yikyoung You; Sangyong No; Gichang Lee; Nokyung Park; Sunkwun Son; Donghee Shin - Web page: https://patentgrep.com/patent/US12190824B2 ## CPC - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G09G 2300/0408: Integration of the drivers onto the display substrate - G09G 2300/0417: Special arrangements specific to the use of low carrier mobility technology - G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/0289: Details of voltage level shifters arranged for use in a driving circuit - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A gate driving circuit includes a capacitor connected between a first gate of a pull-down transistor and a control node, and a control transistor connected between the control node and a ground terminal and having a gate connected to the ground terminal. ## Claims ### Claim 1 A gate driving circuit comprising a plurality of stages, wherein each of the plurality of stages comprises: a signal transmission unit connected between an input terminal to which a start signal is configured to be applied and a first node, and configured to transmit, to the first node, the start signal according to a clock signal; a first inverter configured to control a voltage level of a second node according to a voltage level of the first node; and a second inverter configured to output an output signal of a first voltage of a first voltage level or a second voltage of a second voltage level according to the voltage level of the second node, wherein the second inverter comprises: a first pull-up transistor connected between a first voltage input terminal and an output terminal, and comprising a gate connected to the second node, the first voltage input terminal configured to supply the first voltage; a first pull-down transistor connected between a second voltage input terminal and the output terminal, and comprising a first gate connected to the second node and a second gate connected to a first control node, the second voltage input terminal configured to supply the second voltage; a first capacitor connected between the first gate of the first pull-down transistor and the first control node; and a first control transistor connected between the first control node and a ground terminal and comprising a gate connected to the ground terminal. ### Claim 2 (depends on 1) The gate driving circuit of claim 1, wherein the first pull-down transistor is an N-channel oxide transistor. ### Claim 3 (depends on 2) The gate driving circuit of claim 2, wherein the first gate of the first pull-down transistor is a top gate above a semiconductor layer, and the second gate of the first pull-down transistor is a bottom gate under the semiconductor layer. ### Claim 4 (depends on 1) The gate driving circuit of claim 1, wherein the first inverter comprises: a second pull-up transistor connected between the first voltage input terminal and the second node and comprising a gate connected to the first node; a second pull-down transistor connected between the second voltage input terminal and the second node and comprising a first gate connected to the first node and a second gate connected to a second control node; a second capacitor connected between the first gate of the second pull-down transistor and the second control node; and a second control transistor connected between the second control node and the ground terminal and comprising a gate connected to the ground terminal. ### Claim 5 (depends on 4) The gate driving circuit of claim 4, wherein the second pull-down transistor is an N-channel oxide transistor. ### Claim 6 (depends on 5) The gate driving circuit of claim 5, wherein the first gate of the second pull-down transistor is a top gate above a semiconductor layer, and the second gate of the second pull-down transistor is a bottom gate under the semiconductor layer. ### Claim 7 (depends on 1) The gate driving circuit of claim 1, wherein the signal transmission unit comprises: a first transistor connected between the input terminal and the first node and comprising a gate connected to a second clock terminal; a second transistor connected between the input terminal and the first node and comprising a first gate connected to a first clock terminal and a second gate connected to a third control node; a third capacitor connected between the first gate of the second transistor and the third control node; and a third control transistor connected between the third control node and the ground terminal and comprising a gate connected to the ground terminal. ### Claim 8 (depends on 7) The gate driving circuit of claim 7, wherein a second clock signal configured to be applied to the second clock terminal is an inverted signal of a first clock signal configured to be applied to the first clock terminal. ### Claim 9 (depends on 7) The gate driving circuit of claim 7, wherein the second transistor is an N-channel oxide transistor. ### Claim 10 (depends on 7) The gate driving circuit of claim 7, wherein the first gate of the second transistor is a top gate above a semiconductor layer, and the second gate of the second transistor is a bottom gate under the semiconductor layer. ### Claim 11 (depends on 1) The gate driving circuit of claim 1, further comprising a fourth capacitor connected between the first node and a third voltage supply terminal. ### Claim 12 (depends on 11) The gate driving circuit of claim 11, wherein the third voltage supply terminal is the ground terminal. ### Claim 13 (depends on 11) The gate driving circuit of claim 11, wherein the third voltage supply terminal is configured to receive the first voltage or the second voltage. ### Claim 14 (depends on 1) The gate driving circuit of claim 1, wherein the first pull-up transistor comprises a plurality of sub-transistors connected in parallel between the first voltage input terminal and the output terminal. ### Claim 15 (depends on 1) The gate driving circuit of claim 1, wherein the start signal is an output signal configured to be output from a previous stage. ### Claim 16 A transmission gate circuit comprising: a first transistor connected between an input terminal and an output terminal and comprising a gate connected to a second clock terminal; a second transistor connected between the input terminal and the output terminal and comprising a first gate connected to a first clock terminal and a second gate connected to a control node; a capacitor connected between the first gate of the second transistor and the control node; and a third transistor connected between the control node and a ground terminal and comprising a gate connected to the ground terminal. ### Claim 17 (depends on 16) The transmission gate circuit of claim 16, wherein a second clock signal configured to be applied to the second clock terminal is an inverted signal of a first clock signal configured to be applied to the first clock terminal. ### Claim 18 (depends on 16) The transmission gate circuit of claim 16, wherein the second transistor is an N-channel oxide transistor. ### Claim 19 An inverter circuit comprising: a first transistor connected between a first voltage input terminal to which a first voltage of a first voltage level is configured to be applied and an output terminal, and comprising a gate connected to an input terminal; a second transistor connected between a second voltage input terminal to which a second voltage of a second voltage level is configured to be applied and the output terminal, and comprising a first gate connected to the input terminal and a second gate connected to a control node; a capacitor connected between the first gate of the second transistor and the control node; and a third transistor connected between the control node and a ground terminal and comprising a gate connected to the ground terminal. ### Claim 20 (depends on 19) The inverter circuit of claim 19, wherein the second transistor is an N-channel oxide transistor. ### Claim 21 A gate driving circuit comprising: a transmission circuit configured to receive a clock signal and an inverted clock signal and transmit an input signal to a first node; and an inverter circuit configured to receive a first reference voltage and a second reference voltage and invert and output a voltage level of a voltage of the first node, wherein each of the transmission circuit and the inverter circuit comprises a P-channel transistor and an N-channel transistor, wherein the transmission circuit comprises: a first transistor connected between an input terminal and the first node, and comprising a gate connected to a second clock terminal to which the inverted clock signal is configured to be supplied; a second transistor connected between the input terminal and the first node, and comprising a first gate connected to a first clock terminal to which the clock signal is configured to be supplied and a second gate connected to a first control node; a first capacitor connected between the first gate of the second transistor and the first control node; and a first control transistor connected between the first control node and a ground terminal and comprising a gate connected to the ground terminal, wherein the second transistor is an N-channel transistor. ### Claim 22 (depends on 21) The gate driving circuit of claim 21, wherein the inverter circuit comprises: a first inverter configured to invert a voltage level of a voltage of the first node and output a voltage of the inverted voltage level to a second node; and a second inverter configured to invert a voltage level of a voltage of the second node and output a voltage of the inverted voltage level to an output terminal. ### Claim 23 (depends on 21) The gate driving circuit of claim 21, further comprising a fourth capacitor connected between the first node and a third voltage supply terminal. ### Claim 24 A gate driving circuit comprising: a transmission circuit configured to receive a clock signal and an inverted clock signal and transmit an input signal to a first node; and an inverter circuit configured to receive a first reference voltage and a second reference voltage and invert and output a voltage level of a voltage of the first node, wherein each of the transmission circuit and the inverter circuit comprises a P-channel transistor and an N-channel transistor, wherein the inverter circuit comprises: a first inverter configured to invert a voltage level of a voltage of the first node and output a voltage of the inverted voltage level to a second node; and a second inverter configured to invert a voltage level of a voltage of the second node and output a voltage of the inverted voltage level to an output terminal, wherein the first inverter comprises: a fourth transistor connected between a first voltage input terminal configured to supply the first reference voltage and the second node, and comprising a gate connected to the first node; a fifth transistor connected between a second voltage input terminal configured to supply the second reference voltage and the second node, and comprising a first gate connected to the first node and a second gate connected to a second control node; a second capacitor connected between the first gate of the fifth transistor and the second control node; and a sixth transistor connected between the second control node and a ground terminal and comprising a gate connected to the ground terminal, wherein the fifth transistor is an N-channel transistor. ### Claim 25 A gate driving circuit comprising: a transmission circuit configured to receive a clock signal and an inverted clock signal and transmit an input signal to a first node; and an inverter circuit configured to receive a first reference voltage and a second reference voltage and invert and output a voltage level of a voltage of the first node, wherein each of the transmission circuit and the inverter circuit comprises a P-channel transistor and an N-channel transistor, wherein the inverter circuit comprises: a first inverter configured to invert a voltage level of a voltage of the first node and output a voltage of the inverted voltage level to a second node; and a second inverter configured to invert a voltage level of a voltage of the second node and output a voltage of the inverted voltage level to an output terminal, wherein the second inverter comprises: a seventh transistor connected between a first voltage input terminal configured to supply the first reference voltage and the output terminal, and comprising a gate connected to the second node; an eighth transistor connected between a second voltage input terminal configured to supply the second reference voltage and the output terminal, and comprising a first gate connected to the second node and a second gate connected to a third control node; a third capacitor connected between the first gate of the eighth transistor and the third control node; and a ninth transistor connected between the third control node and a ground terminal and comprising a gate connected to the ground terminal, wherein the eighth transistor is an N-channel transistor.