# US 12,190,810 B2 · Pixel circuit, display device, and driving method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,190,810 B2 - Document ID: US12190810B2 - Status: Granted - Kind: B2 - Application number: 18/255,585 - Filed: 2021-11-26 - Published: 2024-04-04 - Granted: 2025-01-07 - Earliest claimed: 2020-12-09 - Assignees: Sony Semiconductor Solutions Corporation - Applicants: Sony Semiconductor Solutions Corporation - Inventors: Naobumi Toyomura - Web page: https://patentgrep.com/patent/US12190810B2 ## CPC - H10K 59/12: Active-matrix OLED [AMOLED] displays - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2300/0852: being a dynamic memory with more than one capacitor - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/0233: Improving the luminance or brightness uniformity across the screen - G09G 2320/0247: Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes - G09G 2320/045: Compensation of drifts in the characteristics of light emitting or modulating elements - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract Provided are a pixel circuit, a display device, and a driving method that suppress a decrease in luminance. A pixel circuit according to the present disclosure includes a first transistor configured to control a current supplied to a light emitting element according to a voltage supplied to a first terminal, a first capacitor configured to hold the voltage supplied to the first terminal, a second transistor configured to sample a signal voltage of a video signal line, a second capacitor configured to hold the signal voltage sampled by the second transistor, and a third transistor configured to connect the second capacitor and the first capacitor and set a voltage corresponding to the signal voltage to the first capacitor by transferring electric charges accumulated in the second capacitor to the first capacitor. ## Claims ### Claim 1 A pixel circuit, comprising: a first transistor configured to supply, in a light emission period of a first frame of a video signal, a current to a light emitting element based on a first voltage at a specific terminal of the first transistor; a first capacitor configured to hold the first voltage; a second transistor configured to sample, in the light emission period, a signal voltage of a video signal line, wherein the signal voltage corresponds to a second frame of the video signal; a second capacitor configured to hold the sampled signal voltage in the light emission period; and a third transistor configured to: connect the second capacitor to the first capacitor in the second frame and the light emission period; and set, to the first capacitor, a second voltage corresponding to the signal voltage by transfer of electric charges accumulated in the second capacitor to the first capacitor, wherein the electric charges are accumulated in the second capacitor in the light emission period. ### Claim 2 (depends on 1) The pixel circuit according to claim 1, wherein the third transistor is further configured to transfer, to the first capacitor, an amount of the electric charges corresponding to a ratio between the first capacitor and the second capacitor. ### Claim 3 (depends on 1) The pixel circuit according to claim 1, further comprising a fourth transistor configured to: connect the video signal line to a control terminal of the first transistor; receive, from the video signal line, an offset voltage for correction of a threshold of the first transistor; and supply the offset voltage to the control terminal of the first transistor in the second frame, wherein the third transistor is further configured to connect the second capacitor to the first capacitor after end of the correction of the threshold. ### Claim 4 (depends on 1) The pixel circuit according to claim 1, wherein the second transistor and the third transistor are in a well of a silicon substrate, and the specific terminal has a maximum voltage corresponding to a level of luminance among a plurality of levels of luminance, based on a potential of the well that is greater than or equal to the signal voltage. ### Claim 5 (depends on 1) The pixel circuit according to claim 1, further comprising a fifth transistor configured to short-circuit a connection node to a reference voltage, wherein the connection node is between the light emitting element and the first transistor, and the third transistor is further configured to connect the second capacitor to the first capacitor in at least a part of a period in which at least the fifth transistor does not short-circuit the connection node to the reference voltage. ### Claim 6 (depends on 1) The pixel circuit according to claim 1, wherein the specific terminal is a control terminal of the first transistor. ### Claim 7 (depends on 4) The pixel circuit according to claim 4, wherein the first transistor, the second transistor, and the third transistor are P-channel MOS transistors. ### Claim 8 (depends on 4) The pixel circuit according to claim 4, wherein the first transistor, the second transistor, and the third transistor are N-channel MOS transistors. ### Claim 9 (depends on 1) The pixel circuit according to claim 1, further comprising the light emitting element. ### Claim 10 A display device, comprising: a pixel circuit including: a light emitting element; a first transistor configured to supply, in a light emission period of a first frame of a video signal, a current to the light emitting element based on a first voltage at a specific terminal of the first transistor; a first capacitor configured to hold the first voltage; a second transistor configured to sample, in the light emission period, a signal voltage of a video signal line, wherein the signal voltage corresponds to a second frame of the video signal; a second capacitor configured to hold the sampled signal voltage in the light emission period; and a third transistor configured to: connect the second capacitor to the first capacitor in the second frame and the light emission period; and set, to the first capacitor, a second voltage corresponding to the signal voltage by transfer of electric charges accumulated in the second capacitor to the first capacitor, wherein the electric charges are accumulated in the second capacitor in the light emission period; and a drive circuit configured to control an operation of the second transistor and an operation of the third transistor. ### Claim 11 A driving method, comprising: supplying a first voltage held by a first capacitor to a specific first terminal of a first transistor; supplying, by the first transistor, in a light emission period of a first frame of a video signal, a current a light emitting element based on the first voltage supplied to the specific terminal; sampling, by a second transistor, a signal voltage of a video signal line in the light emission period, wherein the signal voltage corresponds to a second frame of the video signal; holding, by a second capacitor, the sampled signal voltage in the light emission period; connecting, by a third transistor, after the signal voltage is held by the second capacitor, the second capacitor to the first capacitor in the second frame and the light emission period; and setting, by the third transistor, a second voltage corresponding to the signal voltage by transferring electric charges accumulated in the second capacitor to the first capacitor, wherein the electric charges are accumulated in the second capacitor in the light emission period. ### Claim 12 A pixel circuit, comprising: a first transistor configured to supply a current to a light emitting element based on a first voltage at a specific terminal of the first transistor; a first capacitor configured to hold the first voltage; a second transistor configured to sample a signal voltage of a video signal line; a second capacitor configured to hold the sampled signal voltage; a third transistor configured to set, to the first capacitor, a second voltage corresponding to the signal voltage by transfer of electric charges accumulated in the second capacitor to the first capacitor; and a fourth transistor configured to short-circuit a connection node to a reference voltage, wherein the connection node is between the light emitting element and the first transistor, and the third transistor is further configured to connect the second capacitor to the first capacitor in at least a part of a period in which at least the fourth transistor does not short-circuit the connection node to the reference voltage.