# US 12,190,780 B2 · GOA circuit and display panel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,190,780 B2 - Document ID: US12190780B2 - Status: Granted - Kind: B2 - Application number: 17/600,332 - Filed: 2021-09-08 - Published: 2024-02-08 - Granted: 2025-01-07 - Earliest claimed: 2021-06-01 - Assignees: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. - Applicants: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. - Inventors: Tuo Feng; Xianjin Ge - Web page: https://patentgrep.com/patent/US12190780B2 ## CPC - G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)} - G09G 3/3677: {suitable for active matrices only} - G09G 3/36: using liquid crystals - G09G 2300/0408: Integration of the drivers onto the display substrate - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract Disclosed are a GOA circuit and a display panel. The gate driver on array circuit comprises a plurality of GOA units, which is cascaded, and a nth stage GOA unit comprises: a pull-down module, pulling down a pull-up control signal and a nth stage gate drive signal to a low potential when the scanning is completed; and a pull-down maintaining module, maintaining the pull-up control signal and the nth stage gate drive signal at the low potential according to a nth stage non-inverting clock signal and a nth inverting clock signal. ## Claims ### Claim 1 A gate driver on array GOA circuit, comprising a plurality of GOA units, which is cascaded, and a nth stage GOA unit comprises: a pull-up control module, outputting a pull-up control signal of a high potential according to a n−bth stage transfer signal and a n−bth stage gate drive signal when scanning starts; an output module, outputting a nth stage gate drive signal of the high potential according to the pull-up control signal of the high potential and a nth stage non-inverting clock signal; a pull-down module, pulling down the pull-up control signal outputted by the pull-up control module and the nth stage gate drive signal outputted by the output module to a low potential according to a n+bth stage gate drive signal when the scanning is completed; and a pull-down maintaining module, maintaining the pull-up control signal outputted by the pull-up control module and the nth stage gate drive signal outputted by the output module at the low potential according to the nth stage non-inverting clock signal and a nth stage inverting clock signal, wherein the nth stage non-inverting clock signal and the nth stage inverting clock signal are mutually inverted signals. ### Claim 2 (depends on 1) The GOA circuit according to claim 1, wherein the pull-down maintaining module comprises a first pull-down maintaining unit and a second pull-down maintaining unit; the pull-down maintaining module is further employed to maintain the pull-up control signal and the nth stage gate drive signal at the low potential by the first pull-down maintaining unit when the nth stage non-inverting clock signal is at the low potential, and the nth stage inverting clock signal is at the high potential; and to maintain the pull-up control signal and the nth stage gate drive signal at the low potential by the second pull-down maintaining unit when the nth stage non-inverting clock signal is at the high potential, and the nth stage inverting clock signal is at the low potential. ### Claim 3 (depends on 2) The GOA circuit according to claim 2, wherein the first pull-down maintaining unit comprises a first switch transistor and a second switch transistor; the first pull-down maintaining unit is employed to control the first switch transistor to turn on according to the nth stage inverting clock signal of the high potential, so as to maintain the nth stage gate drive signal at the low potential, and to control the second switch transistor to be turn on to maintain the pull-up control signal at the low potential; and to control the first switch transistor and the second switch transistor to turn off according to the nth stage inverting clock signal of the low potential. ### Claim 4 (depends on 3) The GOA circuit according to claim 3, wherein the first pull-down maintaining unit further comprises a third switch transistor, a fourth switch transistor, a fifth switch transistor and a sixth switch transistor; a gate and a drain of the third switch transistor are connected to the nth stage inverting clock signal, a source of the third switch transistor is respectively connected to a drain of the fourth switch transistor and a gate of the fifth switch transistor respectively, and a gate of the fourth switch transistor is connected to the pull-up control signal, a source of the fourth switch transistor is connected to a first low potential, and a drain of the fifth switch transistor is connected to the nth stage inverting clock signal, a source of the fifth switch transistor is connected to a drain of the sixth switch transistor, a gate of the first switch transistor and a gate of the second switch transistor respectively, a source of the sixth switch transistor is connected to the first low potential; a drain of the first switch transistor is connected to the nth stage gate drive signal, a source of the first switch transistor is connected to a second low potential, and a drain of the second switch transistor is connected to the pull-up control signal, a source of the second switch transistor is connected to the first low potential. ### Claim 5 (depends on 2) The GOA circuit according to claim 2, wherein the second pull-down maintaining unit comprises a seventh switch transistor and an eighth switch transistor; the second pull-down maintaining unit is employed to control the seventh switch transistor to turn on according to the nth stage non-inverting clock signal of the high potential, so as to maintain the nth stage gate drive signal at the low potential, and to control the eighth switch transistor to turn on to maintain the pull-up control signal at the low potential; and to control the seventh switch transistor and the eighth switch transistor to turn off according to the nth stage non-inverting clock signal of the low potential. ### Claim 6 (depends on 5) The GOA circuit according to claim 5, wherein the second pull-down maintaining unit further comprises a ninth switch transistor, a tenth switch transistor, an eleventh switch transistor and a twelfth switch transistor; a drain and a gate of the ninth switch transistor is connected to the nth stage non-inverting clock signal, a source of the ninth switch transistor is connected to a drain of the tenth switch transistor and a gate of the eleventh switch transistor respectively, and a gate of the tenth switch transistor is connected to the pull-up control signal, a source of the tenth switch transistor is connected to a first low potential; a drain of the eleventh switch transistor is connected to the nth stage non-inverting clock signal, a source of the eleventh switch transistor is connected to a drain of the twelfth switch transistor, a gate of the seventh switch transistor and a gate of the eighth switch transistor respectively, and a gate of the twelfth switch transistor is connected to the pull-up control signal, a source of the twelfth switch transistor is connected to the first low potential; a drain of the seventh switch transistor is connected to the nth stage gate drive signal, a source of the seventh switch transistor is connected to a second low potential; a drain of the eighth switch transistor is connected to the pull-up control signal, a source of the eighth switch transistor is connected to the first low potential. ### Claim 7 (depends on 1) The GOA circuit according to claim 1, wherein the pull-up control module comprises a thirteenth switch transistor; a drain of the thirteenth switch transistor is connected to the n−bth stage gate drive signal, a gate of the thirteenth switch transistor is connected to the n−bth stage transfer signal, a source of the thirteenth switch transistor is connected to the pull-up control signal. ### Claim 8 (depends on 1) The GOA circuit according to claim 1, wherein the output module comprises a fourteenth switch transistor, a fifteenth switch transistor and a bootstrap capacitor; a drain of the fourteenth switch transistor is connected to the nth stage non-inverting clock signal, a gate of the fourteenth switch transistor is connected to the pull-up control signal, one end of the bootstrap capacitor and the other end of the bootstrap capacitor respectively, a source of the fourteenth switch transistor is connected to the nth stage gate drive signal; a drain of the fifteenth switch transistor is connected to the nth stage non-inverting clock signal, a gate of the fifteenth switch transistor is connected to the pull-up control signal, a source of the fifteenth switch transistor is connected to a nth stage transfer signal. ### Claim 9 (depends on 1) The GOA circuit according to claim 1, wherein the pull-down module comprises a sixteenth switch transistor and a seventeenth switch transistor; a drain of the sixteenth switch transistor is connected to the nth stage gate drive signal, a gate of the sixteenth switch transistor is connected to a n+bth stage gate drive signal, a source of the sixteenth switch transistor is connected to a second low potential; a drain of the seventeenth switch transistor is connected to the pull-up control signal, a gate of the seventeenth switch transistor is connected to the n+bth stage gate drive signal, a source of the seventeenth switch transistor is connected to a first low potential. ### Claim 10 A display panel, comprising a gate driver on array GOA circuit, and the GOA circuit comprises a plurality of GOA units, which is cascaded, and a nth stage GOA unit comprises: a pull-up control module, outputting a pull-up control signal of a high potential according to a n−bth stage transfer signal and a n−bth stage gate drive signal when scanning starts; an output module, outputting a nth stage gate drive signal of the high potential according to the pull-up control signal of the high potential and a nth stage non-inverting clock signal; a pull-down module, pulling down the pull-up control signal outputted by the pull-up control module and the nth stage gate drive signal outputted by the output module to a low potential according to a n+bth stage gate drive signal when the scanning is completed; and a pull-down maintaining module, maintaining the pull-up control signal outputted by the pull-up control module and the nth stage gate drive signal outputted by the output module at the low potential according to the nth stage non-inverting clock signal and a nth stage inverting clock signal, wherein the nth stage non-inverting clock signal and the nth stage inverting clock signal are mutually inverted signals. ### Claim 11 (depends on 10) The display panel according to claim 10, wherein the pull-down maintaining module comprises a first pull-down maintaining unit and a second pull-down maintaining unit; the pull-down maintaining module is further employed to maintain the pull-up control signal and the nth stage gate drive signal at the low potential by the first pull-down maintaining unit when the nth stage non-inverting clock signal is at the low potential, and the nth stage inverting clock signal is at the high potential; and to maintain the pull-up control signal and the nth stage gate drive signal at the low potential by the second pull-down maintaining unit when the nth stage non-inverting clock signal is at the high potential, and the nth stage inverting clock signal is at the low potential. ### Claim 12 (depends on 11) The display panel according to claim 11, wherein the first pull-down maintaining unit comprises a first switch transistor and a second switch transistor; the first pull-down maintaining unit is employed to control the first switch transistor to turn on according to the nth stage inverting clock signal of the high potential, so as to maintain the nth stage gate drive signal at the low potential, and to control the second switch transistor to be turn on to maintain the pull-up control signal at the low potential; and to control the first switch transistor and the second switch transistor to turn off according to the nth stage inverting clock signal of the low potential. ### Claim 13 (depends on 12) The display panel according to claim 12, wherein the first pull-down maintaining unit further comprises a third switch transistor, a fourth switch transistor, a fifth switch transistor and a sixth switch transistor; a gate and a drain of the third switch transistor are connected to the nth stage inverting clock signal, a source of the third switch transistor is respectively connected to a drain of the fourth switch transistor and a gate of the fifth switch transistor respectively, and a gate of the fourth switch transistor is connected to the pull-up control signal, a source of the fourth switch transistor is connected to a first low potential, and a drain of the fifth switch transistor is connected to the nth stage inverting clock signal, a source of the fifth switch transistor is connected to a drain of the sixth switch transistor, a gate of the first switch transistor and a gate of the second switch transistor respectively, a source of the sixth switch transistor is connected to the first low potential; a drain of the first switch transistor is connected to the nth stage gate drive signal, a source of the first switch transistor is connected to a second low potential, and a drain of the second switch transistor is connected to the pull-up control signal, a source of the second switch transistor is connected to the first low potential. ### Claim 14 (depends on 11) The display panel according to claim 11, wherein the second pull-down maintaining unit comprises a seventh switch transistor and an eighth switch transistor; the second pull-down maintaining unit is employed to control the seventh switch transistor to turn on according to the nth stage non-inverting clock signal of the high potential, so as to maintain the nth stage gate drive signal at the low potential, and to control the eighth switch transistor to turn on to maintain the pull-up control signal at the low potential; and to control the seventh switch transistor and the eighth switch transistor to turn off according to the nth stage non-inverting clock signal of the low potential. ### Claim 15 (depends on 14) The display panel according to claim 14, wherein the second pull-down maintaining unit further comprises a ninth switch transistor, a tenth switch transistor, an eleventh switch transistor and a twelfth switch transistor; a drain and a gate of the ninth switch transistor is connected to the nth stage non-inverting clock signal, a source of the ninth switch transistor is connected to a drain of the tenth switch transistor and a gate of the eleventh switch transistor respectively, and a gate of the tenth switch transistor is connected to the pull-up control signal, a source of the tenth switch transistor is connected to a first low potential; a drain of the eleventh switch transistor is connected to the nth stage non-inverting clock signal, a source of the eleventh switch transistor is connected to a drain of the twelfth switch transistor, a gate of the seventh switch transistor and a gate of the eighth switch transistor respectively, and a gate of the twelfth switch transistor is connected to the pull-up control signal, a source of the twelfth switch transistor is connected to the first low potential; a drain of the seventh switch transistor is connected to the nth stage gate drive signal, a source of the seventh switch transistor is connected to a second low potential; a drain of the eighth switch transistor is connected to the pull-up control signal, a source of the eighth switch transistor is connected to the first low potential. ### Claim 16 (depends on 10) The display panel according to claim 10, wherein the pull-up control module comprises a thirteenth switch transistor; a drain of the thirteenth switch transistor is connected to the n−bth stage gate drive signal, a gate of the thirteenth switch transistor is connected to the n−bth stage transfer signal, a source of the thirteenth switch transistor is connected to the pull-up control signal. ### Claim 17 (depends on 10) The display panel according to claim 10, wherein the output module comprises a fourteenth switch transistor, a fifteenth switch transistor and a bootstrap capacitor; a drain of the fourteenth switch transistor is connected to the nth stage non-inverting clock signal, a gate of the fourteenth switch transistor is connected to the pull-up control signal, one end of the bootstrap capacitor and the other end of the bootstrap capacitor respectively, a source of the fourteenth switch transistor is connected to the nth stage gate drive signal; a drain of the fifteenth switch transistor is connected to the nth stage non-inverting clock signal, a gate of the fifteenth switch transistor is connected to the pull-up control signal, a source of the fifteenth switch transistor is connected to a nth stage transfer signal. ### Claim 18 (depends on 10) The display panel according to claim 10, wherein the pull-down module comprises a sixteenth switch transistor and a seventeenth switch transistor; a drain of the sixteenth switch transistor is connected to the nth stage gate drive signal, a gate of the sixteenth switch transistor is connected to a n+bth stage gate drive signal, a source of the sixteenth switch transistor is connected to a second low potential; a drain of the seventeenth switch transistor is connected to the pull-up control signal, a gate of the seventeenth switch transistor is connected to the n+bth stage gate drive signal, a source of the seventeenth switch transistor is connected to a first low potential.