# US 12,190,779 B2 · Display system with global emission and method for luminance control thereof

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- Number: US 12,190,779 B2
- Document ID: US12190779B2
- Status: Granted
- Kind: B2
- Application number: 18/061,102
- Filed: 2022-12-02
- Published: 2023-06-15
- Granted: 2025-01-07
- Earliest claimed: 2021-12-09
- Assignees: Micledi Microdisplays BV
- Applicants: Micledi Microdisplays BV
- Inventors: Hamidreza Hashempour; Robbie Thielemans; Soeren Steudel
- Web page: https://patentgrep.com/patent/US12190779B2

## CPC

- G09G 3/2085: {Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination}
- G09G 3/2014: {by modulation of the duration of a single pulse during which the logic level remains constant}
- G09G 3/32: semiconductive, e.g. using light-emitting diodes [LED]
- G09G 3/3258: with pixel circuitry controlling the voltage across the light-emitting element
- G09G 2300/0857: Static memory circuit, e.g. flip-flop
- G09G 2310/0259: with use of an analog or digital ramp generator in the column driver or in the pixel circuit
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2320/064: by time modulation of the brightness of the illumination source
- G09G 2360/12: Frame memory handling
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

A display system is provided that comprises a display panel having a plurality of pixel arrangement. Each pixel arrangement comprises at least one light emitting unit, at least one driver circuit operably coupled to the light emitting unit, and at least one digital counter operably coupled to the driver circuit. In this regard, the digital counter is configured to store a data value to be counted and to toggle a state of the driver circuit upon expiry, thereby toggling a state of the light emitting unit to perform luminance control of the pixel arrangement.

## Claims

### Claim 1

A display system comprising:
a display panel having a plurality of pixel arrangements, and;
a memory unit operably coupled to the plurality of pixel arrangements and disposed external to the display panel; and
wherein each pixel arrangement comprises:
at least one light emitting unit;
at least one driver circuit operably coupled to the light emitting unit; and
a digital counter circuit operably coupled to the at least one driver circuit; and
wherein the memory unit is configured to load a data value to the digital counter circuit of each pixel arrangement, wherein the data value corresponds to respective frame data per pixel of a frame to be displayed,
wherein the digital counter circuit of each pixel arrangement is configured to store the data value, to perform a counting down of the stored data value, and to toggle a state of the at least one driver circuit upon expiry of the digital counter circuit, thereby toggling a state of the light emitting unit to perform luminance control of the pixel arrangement, and
wherein the digital counter circuit of each pixel arrangement comprises a number of M digital counters, where M is an integer, and wherein when M>1 the M digital counters are symmetrically stacked.

### Claim 2 (depends on 1)

The display system according to claim 1, wherein the digital counter circuits are configured to store the data value simultaneously.

### Claim 3 (depends on 2)

The display system according to claim 2, wherein the digital counter circuit of each pixel arrangement is configured to toggle the state of the respective at least one driver circuit based on the respective frame data per pixel of the frame to be displayed.

### Claim 4 (depends on 1)

The display system according to claim 1, wherein each pixel arrangement has a color depth of N-bits and wherein the digital counter circuit of each pixel arrangement is a N-bit digital counter, where N is an integer, and wherein the digital counter circuits of the pixel arrangements are configured to perform the counting down of the respective stored data values simultaneously.

### Claim 5 (depends on 4)

The display system according to claim 4, wherein the digital counter circuit of each pixel arrangement is configured to operate on a clock signal having a frequency determined as a function of a frame rate of the frame to be displayed and the color depth of the respective pixel arrangement.

### Claim 6 (depends on 5)

The display system according to claim 5, wherein a segment of a number of pulses of the clock signal corresponds to a percentage luminance for the respective frame data of the frame to be displayed.

### Claim 7 (depends on 1)

The display system according to claim 1, wherein the memory unit comprises a content-addressable memory configured to provide the respective data value to the digital counter circuit of the respective pixel arrangement simultaneously.

### Claim 8 (depends on 1)

The display system according to claim 1, wherein the light emitting unit comprises a red light emitting element and/or a green light emitting element and/or a blue light emitting element.

### Claim 9 (depends on 1)

The display system according to claim 1, wherein the display panel comprises at least a first wafer and a second wafer, whereby for each pixel arrangement, the light emitting unit is implemented on the first wafer and the at least one driver circuit and the digital counter circuit are implemented on the second wafer, and wherein the first wafer and the second wafer are stacked according to a three-dimensional integration scheme.

### Claim 10 (depends on 1)

The display system according to claim 1, wherein:
for each pixel arrangement, the at least one driver circuit and the M digital counters are implemented on a respective number of M wafers, wherein the at least one light emitting unit is on a separate wafer from the M wafers with the digital counters and the at least one driver circuit, such that when M>1 there are M+1 wafers, and
the separate wafer with the at least one light emitting unit and the M wafers with the digital counters and at least one driver circuit are stacked according to a three-dimensional integration scheme.

### Claim 11

A method for performing luminance control of a display system, the method comprising:
loading a data value into a digital counter of each of a plurality of pixel arrangements of a display panel of the display system from a memory unit disposed external to the display panel, wherein the digital counter circuit of each pixel arrangement comprises a number of M digital counters, where M is an integer, and wherein when M>1 the M digital counters are symmetrically stacked;
storing the data value in the digital counter of each pixel arrangement, wherein the data value corresponds to respective frame data per pixel for a frame to be displayed;
performing a counting down of the stored data value by each digital counter;
toggling a state of a driver circuit of each pixel arrangement upon expiry of the respective digital counter; and
toggling a state of a light emitting unit of each pixel arrangement, based on the state of the respective driver circuit, to perform luminance control of the pixel arrangement.

### Claim 12 (depends on 11)

The method according to claim 11, wherein the storing of the data value in the digital counters occurs simultaneously.

### Claim 13 (depends on 12)

The method according to claim 12, wherein the toggling of the state of the driver circuit of each pixel arrangement is based on the respective frame data per pixel of the frame to be displayed.

### Claim 14 (depends on 11)

The method according to claim 11, wherein the digital counter of each pixel arrangement operates based on a clock signal having a frequency determined as a function of a frame rate of the frame to be displayed and a color depth of the respective pixel arrangement.

### Claim 15 (depends on 11)

The method according to claim 11, wherein the memory unit comprises a content-addressable memory, which provides the data value to the digital counter of each pixel arrangement simultaneously.

### Claim 16 (depends on 11)

The method according to claim 11, wherein, when the digital counter circuit of each pixel arrangement is an N-bit counter implemented as M stacked wafers, each N-bit counter is split into M counters each of K bits and N=M*K.