# US 12,190,766 B2 · Driving circuit and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,190,766 B2 - Document ID: US12190766B2 - Status: Granted - Kind: B2 - Application number: 17/755,867 - Filed: 2022-04-18 - Published: 2024-05-09 - Granted: 2025-01-07 - Earliest claimed: 2022-03-24 - Assignees: Tcl China Star Optoelectronics Technology Co., Ltd. - Applicants: Tcl China Star Optoelectronics Technology Co., Ltd. - Inventors: Jialong Li - Web page: https://patentgrep.com/patent/US12190766B2 ## CPC - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/3674: {Details of drivers for scan electrodes} - G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)} - G09G 3/3266: Details of drivers for scan electrodes - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/0289: Details of voltage level shifters arranged for use in a driving circuit - G09G 2320/043: Preventing or counteracting the effects of ageing - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract The present disclosure discloses a driving circuit and a display device. The driving circuit of the present disclosure inputs a level signal to a first node under the control of a first signal control terminal and a second signal control terminal, and then outputs a signal of a first power supply terminal or a second power supply terminal to the output terminal under the control of the level signal of the first node, so as to output different level signals under the control of two the control signals, thereby resolving a problem that one timing controller cannot be directly matched with different gate driving chips in use. ## Claims ### Claim 1 A driving circuit, comprising: an input module connected to a first signal control terminal, a second signal control terminal, and a first node, respectively, for inputting a level signal to the first node under the control of the first signal control terminal and the second signal control terminal; and an output module connected to a first power supply terminal, a second power supply terminal, the first node, and an output terminal, respectively, for outputting a signal of the first power supply terminal or the second power supply terminal to the output terminal under the control of the level signal of the first node. ### Claim 2 (depends on 1) The driving circuit of claim 1, wherein the input module includes: a first transistor, wherein a gate of the first transistor is connected to the first signal control terminal, one of a source and a drain of the first transistor is connected to the second signal control terminal, and another of the source electrode and the drain electrode of the first transistor is connected to the first node; and a second transistor, wherein a gate of the second transistor is connected to the first signal control terminal, one of a source and a drain of the second transistor is connected to the second signal control terminal, and another of the source electrode and the drain electrode of the second transistor is connected to the first node; wherein the first transistor is one of a P-type transistor and an N-type transistor, and the second transistor is another of the P-type transistor and the N-type transistor. ### Claim 3 (depends on 2) The driving circuit of claim 2, wherein the input module further includes: a fifth transistor, wherein a gate of the fifth transistor is connected to a second node, one of a source and a drain of the fifth transistor is connected to a third power supply terminal, and another of the source electrode and the drain electrode of the fifth transistor is connected to the first node; and a sixth transistor, wherein a gate of the sixth transistor is connected to the second node, one of a source and a drain of the sixth transistor is connected to a fourth power supply terminal, and another of the source electrode and the drain electrode of the sixth transistor is connected to the first node; wherein another of the source electrode and the drain electrode of the first transistor is connected to the second node, the fifth transistor is one of a P-type transistor and an N-type transistor, and the sixth transistor is another of the P-type transistor and the N-type transistor. ### Claim 4 (depends on 3) The driving circuit of claim 3, wherein, the first power supply terminal and the third power supply terminal are the same power supply terminal; and the second power supply terminal and the fourth power supply terminal are the same power supply terminal. ### Claim 5 (depends on 4) The driving circuit of claim 4, wherein, the signals of the first power supply terminal and the third power supply terminal are a high level signal or a low level signal, and the signals of the second power supply terminal and the fourth power supply terminal are a low level signal or a high level signal. ### Claim 6 (depends on 3) The driving circuit of claim 3, wherein, the first power supply terminal and the fourth power supply terminal are the same power supply terminal; and the second power supply terminal and the third power supply terminal are the same power supply terminal. ### Claim 7 (depends on 6) The driving circuit of claim 6, wherein, the signals of the first power supply terminal and the fourth power supply terminal are a high level signal or a low level signal, and the signals of the second power supply terminal and the third power supply terminal are a low level signal or a high level signal. ### Claim 8 (depends on 1) The driving circuit of claim 1, wherein the output module includes: a third transistor, wherein a gate of the third transistor is connected to the first node, one of a source and a drain of the third transistor is connected to the first power supply terminal, and another of the source electrode and the drain electrode of the second transistor is connected to the output terminal; and a fourth transistor, wherein a gate of the fourth transistor is connected to the first node, one of a source and a drain of the fourth transistor is connected to the second power supply terminal, and another of the source electrode and the drain electrode of the fourth transistor is connected to the output terminal; wherein the third transistor is one of a P-type transistor and an N-type transistor, and the fourth transistor is another of the P-type transistor and the N-type transistor. ### Claim 9 (depends on 8) The driving circuit of claim 8, wherein the input module includes: a seventh transistor, wherein a gate of the seventh transistor is connected to a third node, one of a source and a drain of the seventh transistor is connected to a fourth node, and another of the source electrode and the drain electrode of the seventh transistor is connected to the output terminal; and an eighth transistor, wherein a gate of the eighth transistor is connected to the third node, one of a source and a drain of the sixth transistor is connected to the fourth node, and another of the source electrode and the drain electrode of the eighth transistor is connected to the output terminal; wherein, another of the source and the drain of the third transistor is connected to the fourth node, and another of the source electrode and the drain electrode of the fourth transistor is connected to the fourth node; wherein the first signal control terminal is connected to the third node, the seventh transistor is one of a P-type transistor and an N-type transistor, and the eighth transistor is another of the P-type transistor and the N-type transistor. ### Claim 10 (depends on 8) The driving circuit of claim 8, wherein the output module includes: a seventh transistor, wherein a gate of the seventh transistor is connected to a third node, one of a source and a drain of the seventh transistor is connected to a fourth node, and another of the source electrode and the drain electrode of the seventh transistor is connected to the output terminal; and an eighth transistor, wherein a gate of the eighth transistor is connected to the third node, one of a source and a drain of the sixth transistor is connected to the fourth node, and another of the source electrode and the drain electrode of the eighth transistor is connected to the output terminal; wherein, another of the source and the drain of the third transistor is connected to the fourth node, and another of the source electrode and the drain electrode of the fourth transistor is connected to the fourth node; wherein, the second signal control terminal is connected to the third node, the seventh transistor is one of a P-type transistor and an N-type transistor, and the eighth transistor is another of the P-type transistor and the N-type transistor. ### Claim 11 A display device comprising a driving circuit, wherein the driving circuit includes: an input module connected to a first signal control terminal, a second signal control terminal, and a first node, respectively, for inputting a level signal to the first node under the control of the first signal control terminal and the second signal control terminal; and an output module connected to a first power supply terminal, a second power supply terminal, the first node, and an output terminal, respectively, for outputting a signal of the first power supply terminal or the second power supply terminal to the output terminal under the control of the level signal of the first node. ### Claim 12 (depends on 11) The display device of claim 11, further comprising: a timing controller connected to the first signal control terminal and the second signal control terminal of the driving circuit; and a gate driving chip connected to the output terminal of the driving circuit. ### Claim 13 (depends on 11) The display device of claim 11, wherein the input module includes: a first transistor, wherein a gate of the first transistor is connected to the first signal control terminal, one of a source and a drain of the first transistor is connected to the second signal control terminal, and another of the source electrode and the drain electrode of the first transistor is connected to the first node; and a second transistor, wherein a gate of the second transistor is connected to the first signal control terminal, one of a source and a drain of the second transistor is connected to the second signal control terminal, and another of the source electrode and the drain electrode of the second transistor is connected to the first node; wherein the first transistor is one of a P-type transistor and an N-type transistor, and the second transistor is another of the P-type transistor and the N-type transistor. ### Claim 14 (depends on 13) The display device of claim 13, wherein the input module includes: a fifth transistor, wherein a gate of the fifth transistor is connected to a second node, one of a source and a drain of the fifth transistor is connected to a third power supply terminal, and another of the source electrode and the drain electrode of the fifth transistor is connected to the first node; and a sixth transistor, wherein a gate of the sixth transistor is connected to the second node, one of a source and a drain of the sixth transistor is connected to a fourth power supply terminal, and another of the source electrode and the drain electrode of the sixth transistor is connected to the first node; wherein another of the source electrode and the drain electrode of the first transistor is connected to the second node, the fifth transistor is one of a P-type transistor and an N-type transistor, and the sixth transistor is another of the P-type transistor and the N-type transistor. ### Claim 15 (depends on 14) The display device of claim 14, wherein, the first power supply terminal and the third power supply terminal are the same power supply terminal; and the second power supply terminal and the fourth power supply terminal are the same power supply terminal. ### Claim 16 (depends on 15) The display device of claim 15, wherein, the signals of the first power supply terminal and the third power supply terminal are a high level signal or a low level signal, and the signals of the second power supply terminal and the fourth power supply terminal are a low level signal or a high level signal. ### Claim 17 (depends on 14) The display device of claim 14, wherein, the first power supply terminal and the fourth power supply terminal are the same power supply terminal; and the second power supply terminal and the third power supply terminal are the same power supply terminal. ### Claim 18 (depends on 11) The display device of claim 11, wherein the output module includes: a third transistor, wherein a gate of the third transistor is connected to the first node, one of a source and a drain of the third transistor is connected to the first power supply terminal, and another of the source electrode and the drain electrode of the second transistor is connected to the output terminal; and a fourth transistor, wherein a gate of the fourth transistor is connected to the first node, one of a source and a drain of the fourth transistor is connected to the second power supply terminal, and another of the source electrode and the drain electrode of the fourth transistor is connected to the output terminal; wherein the third transistor is one of a P-type transistor and an N-type transistor, and the fourth transistor is another of the P-type transistor and the N-type transistor. ### Claim 19 (depends on 18) The display device of claim 18, wherein the output module includes: a seventh transistor, wherein a gate of the seventh transistor is connected to a third node, one of a source and a drain of the seventh transistor is connected to a fourth node, and another of the source electrode and the drain electrode of the seventh transistor is connected to the output terminal; and an eighth transistor, wherein a gate of the eighth transistor is connected to the third node, one of a source and a drain of the sixth transistor is connected to the fourth node, and another of the source electrode and the drain electrode of the eighth transistor is connected to the output terminal; wherein, another of the source and the drain of the third transistor is connected to the fourth node, and another of the source electrode and the drain electrode of the fourth transistor is connected to the fourth node; wherein the first signal control terminal is connected to the third node, the seventh transistor is one of a P-type transistor and an N-type transistor, and the eighth transistor is another of the P-type transistor and the N-type transistor. ### Claim 20 (depends on 18) The display device of claim 18, wherein the output module further includes: a seventh transistor, wherein a gate of the seventh transistor is connected to a third node, one of a source and a drain of the seventh transistor is connected to a fourth node, and another of the source electrode and the drain electrode of the seventh transistor is connected to the output terminal; and an eighth transistor, wherein a gate of the eighth transistor is connected to the third node, one of a source and a drain of the sixth transistor is connected to the fourth node, and another of the source electrode and the drain electrode of the eighth transistor is connected to the output terminal; wherein, another of the source and the drain of the third transistor is connected to the fourth node, and another of the source electrode and the drain electrode of the fourth transistor is connected to the fourth node; wherein, the second signal control terminal is connected to the third node, the seventh transistor is one of a P-type transistor and an N-type transistor, and the eighth transistor is another of the P-type transistor and the N-type transistor.