Rounding hexadecimal floating point numbers using binary incrementors
AssigneeInternational Business Machines Corporation
InventorsMichael Klein, Petra Leber, Cedric Lichtenau, Stefan Payer, Kerstin Claudia Schelm
Life of this patent
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Abstract
Rounding hexadecimal floating point numbers using binary incrementors, including: incrementing, by a first incrementor, a first subset of bits of an operand comprising a binary hexadecimal floating point operand; incrementing, by a second incrementor, a second subset of bits of the operand; generate an intermediate result based on a carryout of the second incrementor; and generate an incremented result based on a carryout of the first incrementor and one or more of: a first bit of the intermediate result or the carryout of the second incrementor.
Claims20
A method of rounding hexadecimal floating point numbers using binary incrementors, the method comprising:
- incrementing, by a first incrementor, a first subset of bits of an operand comprising a binary hexadecimal floating point operand;
- incrementing, by a second incrementor, a second subset of bits of the operand;
- generating, by a multiplexor, an intermediate result based on a carryout of the second incrementor;
- generating, by correction logic if a carryout of the first incrementor is set, an incremented result based on the carryout of the first incrementor and one or more of:
- a first bit of the intermediate result or the carryout of the second incrementor;
- and
- generating, by the correction logic if the carryout of the first incrementor is not set, the incremented result based on whether the first bit of the intermediate result is set.
A chip for rounding hexadecimal floating point numbers using binary incrementors, comprising:
- a first incrementor;
- a second incrementor;
- correction logic;
- and
- a multiplexor, wherein:
- the first incrementor increments a first subset of bits of an operand comprising a binary hexadecimal floating point operand;
- the second incrementor increments a second subset of bits of the operand;
- the multiplexor receives a non-incremented first subset of bits and the incremented first subset of bits and generates an intermediate result based on a carryout of the second incrementor;
- the correction logic generates an incremented result if a carryout of the first incrementor is set based on the carryout of the first incrementor and one or more of:
- a first bit of the intermediate result or the carryout of the second incrementor;
- and
- the correction logic generates the incremented result if the carryout of the first incrementor is not set based on whether the first bit of the intermediate result is set.
An apparatus for comprising:
- a processor;
- and
- memory coupled to the processor, wherein the processor comprises:
- a first incrementor;
- a second incrementor;
- correction logic;
- and
- a multiplexor, and wherein:
- the first incrementor increments a first subset of bits of an operand comprising a binary hexadecimal floating point operand;
- the second incrementor increments a second subset of bits of the operand;
- the multiplexor receives a non-incremented first subset of bits and the incremented first subset of bits and generates an intermediate result based on a carryout of the second incrementor;
- the correction logic generates an incremented result if a carryout of the first incrementor is set based on the carryout of the first incrementor and one or more of:
- a first bit of the intermediate result or the carryout of the second incrementor;
- and
- the correction logic generates the incremented result if the carryout of the first incrementor is not set based on whether the first bit of the intermediate result is set.
Dependencies are inferred from the claim text.