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US 12,189,571 B2Granted
Dual pipeline parallel systolic array
AssigneeIntel Corporation
InventorsJorge Parra, Jiasheng Chen, Supratim Pal, Fangwen Fu, Sabareesh Ganapathy, Chandra Gurram, Chunhui Mei, Yue Qi
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Abstract
A processing apparatus described herein includes a general-purpose parallel processing engine comprising a systolic array having multiple pipelines, each of the multiple pipelines including multiple pipeline stages, wherein the multiple pipelines include a first pipeline, a second pipeline, and a common input shared between the first pipeline and the second pipeline.
Claims20
A processing apparatus including:
- a general-purpose parallel processing engine comprising a systolic array having multiple pipelines, each of the multiple pipelines including multiple pipeline stages, wherein the multiple pipelines include a first pipeline, a second pipeline, and a common input shared between the first pipeline and the second pipeline, and
- wherein the systolic array includes a first output memory associated with the first pipeline, a second output memory associated with the second pipeline, and common output circuitry configurable to output from one of the first output memory and the second output memory.
A method comprising:
- fetching an instruction at a processing resource of a graphics processor to perform operations associated with a matrix instruction, the processing resource including a systolic array having multiple pipelines, each of the multiple pipelines including multiple pipeline stages, wherein the multiple pipelines include a first pipeline, a second pipeline, and a common input shared between the first pipeline and the second pipeline;
- decoding the instruction into multiple sub-instructions;
- reading operand data for the sub-instructions from a register file of the processing resource, the operand data including matrix elements associated with the multiple sub-instructions;
- executing a first set of the multiple sub-instructions via the first pipeline and concurrently executing the second set of the multiple sub-instructions via the second pipeline;
- and
- writing output of the first set of the multiple sub-instructions and the second set of the multiple sub-instructions to the register file, including:
- writing output from the first pipeline to a first output buffer associated with the first pipeline;
- writing output from the second pipeline to a second output buffer associated with the second pipeline;
- and
- writing output from the first output buffer and the second output buffer to the register file via a common output.
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A system comprising:
- a memory device;
- and
- a graphics processor coupled to the memory device, the graphics processor comprising a general-purpose parallel processing engine including:
- a matrix accelerator including:
- multiple pipelines of processing elements, each of the multiple pipelines including multiple pipeline stages, wherein the multiple pipelines include a first pipeline, a second pipeline, and a common input shared between the first pipeline and the second pipeline, the common input associated with column data for a matrix multiply operation;
- a first output memory associated with the first pipeline;
- a second output memory associated with the second pipeline;
- and
- common output circuitry configurable to output from one of the first output memory and the second output memory.
6 more elements
Dependencies are inferred from the claim text.