Error protection analysis of an integrated circuit

An apparatus for error protection analysis of an integrated circuit, the apparatus comprising:

• a computer processor;
• and
• a computer memory operatively coupled to the computer processor, the computer memory having disposed therein computer program instructions that, when executed by the computer processor, cause the apparatus to:
• receive a design model for the integrated circuit and a list of error checkers associated with the design model;
• traverse the design model from each of the error checkers to group storage cells of the design model into checking groups;
• and
• update the design model to include, for each checking group, a unique group identifier associated with each of the storage cells in the checking group.

A computer program product for error protection analysis of an integrated circuit, the computer program product disposed upon a computer readable medium, the computer program product comprising computer program instructions that, when executed, cause a computer to:

• receive a design model for the integrated circuit and a list of error checkers associated with the design model;
• traverse the design model from each of the error checkers to group storage cells of the design model into checking groups;
• and
• update the design model to include, for each checking group, a unique group identifier associated with each of the storage cells in the checking group.