Wide-range inductor-based delay-cell and area efficient termination switch control

A quadrature generator apparatus comprising:

• a I-path to generate an I-clock;
• a Q-path to generate Q-clock, wherein the Q-clock is substantially 90 phase-shifted relative to the I-clock;
• and
• a node coupled to the I-path and the Q-path, wherein the node is to receive an input clock;
• wherein the I-path comprises:
• an inverter;
• a first switch capacitor with adjustable capacitance, the first switch coupled to an output of the inverter;
• a resistor based digital-to-analog converter (R-DAC);
• a second switch capacitor with adjustable capacitance;
• and
• a shunt-series set of inductors comprising a shunt inductor coupled to the R-DAC, and a series inductor coupled to the first switch capacitor and the second switch capacitor.

A computing system with a quadrature generator, comprising:

• a processor;
• a wireless interface to allow the processor to communicate with another device;
• and
• a memory coupled to the processor, wherein the processor includes a serial-deserializer transmitter which includes a clock buffer which comprises:
• a first driver to receive a first input and having a first output;
• a second driver to receive a second input and having a second output, wherein the first input is complementary of the second input;
• a first shunt-series set of inductors coupled to the first output;
• and
• a second shunt-series set of inductors coupled to the second output, wherein the first shunt-series set of inductors is coupled to the second shunt-series set of inductors via a resistor based digital-to-analog converter (R-DAC).