# US 12,184,307 B2 · Mitigating DBI bit flip induced errors

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- Number: US 12,184,307 B2
- Document ID: US12184307B2
- Status: Granted
- Kind: B2
- Application number: 17/646,378
- Filed: 2021-12-29
- Published: 2023-06-29
- Granted: 2024-12-31
- Earliest claimed: 2021-12-29
- Assignees: SanDisk Technologies LLC
- Applicants: Western Digital Technologies, Inc.
- Inventors: Shay Benisty; Judah Gamliel Hahn; Ariel Navon
- Web page: https://patentgrep.com/patent/US12184307B2

## CPC

- H03M 13/45: Soft decoding, i.e. using symbol reliability information (H03M13/41 takes precedence)
- G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)}
- H03M 13/353: {Adaptation to the channel}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 7/1048: {Data bus control circuits, e.g. precharging, presetting, equalising}
- H03M 13/1111: {Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present disclosure generally relates to improving data transfer in a data storage device. In double data rate (DDR) systems that include a data bus inversion (DBI) functionality, bit flip events can be more prevalent. To mitigate the effect of enhanced erroneous bit flip rate related to DBI bit flip events, the DBI bit can stay static for a predetermined number of consecutive clock cycles, the error correction module can be informed of reduced reliability due to active DBI bit events, the DBI bit can be set to 0, or combinations thereof. Setting the DBI bit to 0 effectively cancels DBI functionality. Informing the error correction module permits a more robust error correction to occur. Forcing the DBI bit to remain static reduces the probability of an unrecognized bit flip event of a full byte. In so doing, data transfer reliability is improved when using DBI functionality.

## Claims

### Claim 1

A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
receive data from a host device;
arrange the data into one or more bursts, wherein each burst comprises a plurality of bytes;
set a data bus inversion (DBI) bit for each byte, wherein a plurality of consecutive DBI bits within at least one burst of the one or more bursts are identical, and wherein the plurality of consecutive DBI bits that are identical corresponds to a predetermined number of clock cycles;
send the one or more bursts and DBI bits to the memory device;
send a first reliability indication to the memory device, wherein the first reliability indication is based on a search of a log likelihood ratio (LLR) table of the received data;
send a second reliability indication to the memory device, wherein the second reliability indication is based on a search of a DBI LLR table of the DBI bit; and
determine a decoding level based upon the first and second reliability indicator.

### Claim 2 (depends on 1)

The data storage device of claim 1, wherein the DBI bits are sent in a separate channel from the data in the one or more bursts.

### Claim 3 (depends on 1)

The data storage device of claim 1, wherein during each clock cycle, one byte and one DBI bit is sent to the memory device.

### Claim 4 (depends on 1)

The data storage device of claim 1, wherein the DBI bit is a bit that is distinct from bits of the plurality of bytes.

### Claim 5 (depends on 1)

The data storage device of claim 1, wherein the controller is configured to manipulate the data prior to sending the one or more bursts, wherein the manipulating comprises flipping bits in one or more bytes of the plurality of bytes.

### Claim 6 (depends on 5)

The data storage device of claim 5, wherein flipping bits comprises flipping bits such that a DBI bit for a byte corresponding to the flipped bits can be set to 1.

### Claim 7 (depends on 5)

The data storage device of claim 5, wherein flipping bits comprises flipping bits such that a DBI bit for a byte corresponding to the flipped bits can be set to 0.

### Claim 8 (depends on 1)

The data storage device of claim 1, wherein setting the DBI bit for each byte comprises setting the DBI bit to 0.

### Claim 9 (depends on 1)

The data storage device of claim 1, wherein the plurality of consecutive DBI bits is based upon a threshold.

### Claim 10 (depends on 9)

The data storage device of claim 9, wherein the threshold when transitioning from 1 to 0 is different than the threshold when transitioning from 0 to 1.

### Claim 11 (depends on 9)

The data storage device of claim 9, wherein the threshold is dynamic.

### Claim 12

A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
retrieve data from the memory device;
send retrieved data to a decoder;
search a log likelihood ratio (LLR) table for a first reliability indication of the retrieved data;
send a data bus inversion (DBI) bit associated with the retrieved data to a DBI LLR adaptation module, wherein the DBI LLR adaptation module comprises a DBI LLR table;
search the DBI LLR table for a second reliability indication of the DBI bit;
send the first reliability indication and the second reliability indication to the decoder for the retrieved data;
decode the retrieved data;
determine a decode level to perform based on the first and second reliability indication; and
force a DBI bit to remain constant for a predetermined number of consecutive clock cycles.

### Claim 13 (depends on 12)

The data storage device of claim 12, wherein the controller is further configured to provide an indication to the decoder that a byte to be read has an active DBI bit event.

### Claim 14 (depends on 13)

The data storage device of claim 13, wherein an active DBI event comprises determining that a DBI bit value is a different value from an adjacent DBI bit value.

### Claim 15 (depends on 13)

The data storage device of claim 13, wherein the decoder is a part of an error correction module, wherein the error correction module additionally comprises the LLR table and the DBI LLR adaptation module.