Single-ended analog signal receiver apparatus

A single-ended analog signal receiver apparatus for receiving a single-ended analog signal from an input signal terminal and outputting an output signal relative to a local ground terminal at an output terminal, the single-ended analog signal receiver apparatus comprising:

• a buffer gain unit comprising:
• a first buffer gain input terminal and a second buffer gain input terminal;
• a first buffer gain output terminal and a second buffer gain output terminal,
• a first bias resistor and a second bias resistor connected in series between the first buffer gain input terminal and the second buffer gain input terminal of the buffer gain unit;
• a third bias resistor connected between a node between the first bias resistor and the second bias resistor and the local ground terminal;
• a fourth bias resistor connected between the input signal terminal of the single-ended analog signal receiver apparatus and the first buffer gain input terminal of the buffer gain unit;
• a fifth bias resistor connected between an input reference terminal of the single-ended analog signal receiver apparatus and the second buffer gain input terminal of the buffer gain unit;
• a sixth bias resistor and a seventh bias resistor connected in series between the first buffer gain output terminal and the second buffer gain output terminal of the buffer gain unit;
• a unity-gain amplifier unit comprising an input terminal and an output terminal, wherein the input terminal of the unity-gain amplifier unit is connected to a node between the sixth and seventh bias resistors;
• a first capacitor connected between the output terminal of the unity-gain amplifier unit and a node between the first, second, and third bias resistors, the first capacitor being sized to have an impedance less than a resistance value of the third bias resistor at a frequency higher than a first predetermined frequency;
• a second capacitor and a third capacitor connected in series between the input signal terminal and the input reference terminal of the unity-gain amplifier unit;
• a fourth capacitor connected between a node between the second capacitor and the third capacitor and the local ground terminal;
• and
• an eighth bias resistor connected between the output terminal of the unity-gain amplifier unit and a node between the second, third, and fourth capacitors, the fourth capacitor being sized to have an impedance less than a resistance value of the eighth bias resistor at a frequency lower than a second predetermined frequency,
• a post-stage balance circuit unit with common mode rejection comprising:
• a first post-stage input terminal and a second post-stage input terminal connected to the first buffer gain output terminal and the second buffer gain output terminal of the buffer gain unit, respectively;
• and
• a post-stage output terminal connected to the output terminal of the single-ended analog signal receiver apparatus.