# US 12,184,300 B2 · Duty-cycle-correcting clock distribution architecture

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- Number: US 12,184,300 B2
- Document ID: US12184300B2
- Status: Granted
- Kind: B2
- Application number: 18/494,731
- Filed: 2023-10-25
- Published: 2024-04-11
- Granted: 2024-12-31
- Earliest claimed: 2020-05-14
- Assignees: Gigajot Technology, Inc.
- Applicants: Gigajot Technology, Inc.
- Inventors: Dexue Zhang
- Web page: https://patentgrep.com/patent/US12184300B2

## CPC

- H03M 1/38: sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14)
- H03K 5/1565: {the output pulses having a constant duty cycle}
- H03M 1/56: Input signal compared with linear ramp
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Clock and other cyclical signals are driven onto respective capacitively-loaded segments of a distribution path via inverting buffer stages that self-correct for stage-to-stage duty cycle error, yielding a balanced signal duty cycle over the length of the distribution path.

## Claims

### Claim 1

An integrated-circuit image sensor comprising:
a pixel array that includes a plurality of pixel elements, wherein outputs of the pixel elements are controlled by a clock signal; and
a clock distribution circuitry that distributes the clock signal to respective count-value elements configured to receive the clock signal along a signal distribution path, wherein the clock distribution circuitry is configured to:
alternately generate inverted and non-inverted instances of the clock signal on successive segments of the signal distribution path;
route the inverted instances of the clock signal to first count-value elements via circuitry that complements the inverted instances of the clock signal; and
route the non-inverted instances of the clock signal to second count-value elements without complementing the non-inverted instances,
wherein the alternate generation of the inverted and non-inverted instances of the clock signal avoids propagation of a cumulative distortion of the clock signal along the signal distribution path.

### Claim 2 (depends on 1)

The integrated-circuit image sensor of claim 1, wherein the clock signal has a cycle time of a nanosecond or less.

### Claim 3 (depends on 1)

The integrated-circuit image sensor of claim 1, wherein the clock distribution circuitry is implemented as part of a readout circuitry of the pixel array.

### Claim 4 (depends on 3)

The integrated-circuit image sensor of claim 3, wherein the clock signal is generated by a clock generator implemented as part of a signal process controller of the readout circuitry.

### Claim 5 (depends on 1)

The integrated-circuit image sensor of claim 1, wherein the clock signal is a 50% duty-cycle clock signal.

### Claim 6 (depends on 1)

The integrated-circuit image sensor of claim 1, wherein the clock distribution circuitry includes a pull-up transistor that generates a rising edge in the clock signal and a pull-down transistor that generates a falling edge of the clock signal, wherein the pull-up and pull-down transistors have unequal slew rates to cause a duty-cycle distortion in the clock signal.

### Claim 7 (depends on 6)

The integrated-circuit image sensor of claim 6, wherein the clock distribution circuitry causes a first duty-cycle distortion of the clock signal added at a first buffer stage of the signal distribution path to be reversed by a complement duty-cycle distortion of the clock signal added by a next buffer stage of the signal distribution path after the first buffer stage.

### Claim 8 (depends on 1)

The integrated-circuit image sensor of claim 1, wherein pixel array is a megapixel sensor array.

### Claim 9 (depends on 1)

The integrated-circuit image sensor of claim 1, wherein pixel array is a gigapixel sensor array.

### Claim 10 (depends on 1)

The integrated-circuit image sensor of claim 1, wherein multiple ones of the first count-value elements are grouped into a counter group that is inverted by a single local inverter associated with the counter group.

### Claim 11

A method comprising:
performing, by an integrated-circuit image sensor:
generating a clock signal used to control outputs of a plurality of pixel elements in a pixel array;
distributing, via a clock distribution circuitry, the clock signal to respective count-value elements along a signal distribution path, wherein the distributing includes:
alternately generating inverted and non-inverted instances of the clock signal on successive segments of the signal distribution path;
routing the inverted instances of the clock signal to first count-value elements via circuitry that complements the inverted instances of the clock signal; and
routing the non-inverted instances of the clock signal to second count-value elements without complementing the non-inverted instances,
wherein the alternately generating of the inverted and non-inverted instances of the clock signal avoids propagation of a cumulative distortion of the clock signal along the signal distribution path.

### Claim 12 (depends on 11)

The method of claim 11, wherein the clock signal has a cycle time of a nanosecond or less.

### Claim 13 (depends on 11)

The method of claim 11, wherein the clock distribution circuitry is implemented as part of a readout circuitry of the pixel array.

### Claim 14 (depends on 13)

The method of claim 13, wherein the clock signal is generated by a clock generator, and the clock generator is implemented as part of a signal process controller of the readout circuitry.

### Claim 15 (depends on 11)

The integrated-circuit image sensor of claim 11, wherein the clock signal is a 50% duty-cycle clock signal.

### Claim 16 (depends on 11)

The method of claim 11, further comprising:
causing a pull-up transistor to generate a rising edge in the clock signal;
causing a pull-down transistor to generate a falling edge of the clock signal,
wherein the pull-up and pull-down transistors have unequal slew rates to cause a duty-cycle distortion in the clock signal.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
causing a first duty-cycle distortion of the clock signal at a first buffer stage of the signal distribution path;
causing a complement duty-cycle distortion of the clock signal at a next buffer stage of the signal distribution path after the first buffer stage, wherein the complement duty-cycle distortion reverses the first duty-cycle distortion.

### Claim 18 (depends on 11)

The method of claim 11, wherein pixel array is a megapixel sensor array.

### Claim 19 (depends on 11)

The method of claim 11, wherein pixel array is a gigapixel sensor array.

### Claim 20 (depends on 11)

The method of claim 11, wherein multiple ones of the first count-value elements are grouped into a counter group, and the complementing of the inverted instances of the clock signal received by the multiple count-value elements is performed by a single local inverter associated with the counter group.