Configuration of ADC data rates across multiple physical channels
AssigneeAyDee Kay LLC
InventorsSetu Mohta, Christopher A. Menkus, David Kang
Life of this patent
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AssigneeAyDee Kay LLC
InventorsSetu Mohta, Christopher A. Menkus, David Kang
Estimating the term…
An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.
An analog-to-digital converter (ADC), comprising:
An electronic device, comprising an analog-to-digital converter (ADC), wherein the ADC comprises:
A method for selecting one or more subsets of a set of N unit analog-to-digital converters (ADCs), comprising:
Dependencies are inferred from the claim text.