# US 12,184,297 B2 · Fault detection within an analog-to-digital converter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,184,297 B2 - Document ID: US12184297B2 - Status: Granted - Kind: B2 - Application number: 18/159,305 - Filed: 2023-01-25 - Published: 2023-05-25 - Granted: 2024-12-31 - Earliest claimed: 2021-09-23 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Veeramanikandan Raju; Anand Kumar G - Web page: https://patentgrep.com/patent/US12184297B2 ## CPC - H03M 1/0604: {at one point, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18)} - H03M 1/126: {Multi-rate systems, i.e. adaptive to different fixed sampling rates} - H03M 1/0678: {using additional components or elements, e.g. dummy components} - H03M 1/122: {Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs; a window comparator that compares a digital value output by the ADC to first and second threshold values defining a window and that asserts a trigger signal in response to the digital value being outside the window; a programmable clock circuit that provides a clock signal to the ADC; a controller that generates, in response to assertion of the trigger signal, a sample rate control signal to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs; and comparison circuitry that compares a first digital output from the ADC to a second digital output from the ADC. ## Claims ### Claim 1 A circuit comprising: a controller configured to generate a sample rate control signal; a programmable clock circuit configured to output a clock signal at a first frequency in response to the sample rate control signal being in a first logic state, and to output the clock signal at a second frequency in response to the sample rate control signal being in a second logic state; an analog-to-digital converter (ADC) configured to receive the clock signal and to output first and second digital values; and comparison circuitry configured to compare the first digital value to the second digital value. ### Claim 2 (depends on 1) The circuit of claim 1, further comprising: a window comparator configured to generate a trigger signal in response to a comparison of a digital value output from the ADC to first and second thresholds. ### Claim 3 (depends on 2) The circuit of claim 2, wherein the controller is configured to assert the sample rate control signal in response to a logic state of the trigger signal. ### Claim 4 (depends on 2) The circuit of claim 2, wherein the controller is configured to generate and output a channel select signal in response to a logic state of the trigger signal. ### Claim 5 (depends on 1) The circuit of claim 1, wherein the second frequency is twice the first frequency. ### Claim 6 (depends on 2) The circuit of claim 2, wherein the controller is configured to disable the window comparator in response to the trigger signal. ### Claim 7 (depends on 1) The circuit of claim 1, wherein the comparison circuitry is configured to receive an error tolerance signal and compare an absolute difference between the first and second digital values to the error tolerance signal. ### Claim 8 (depends on 7) The circuit of claim 7, wherein the comparison circuitry is configured to generate a safety fault in response to the absolute difference being greater than the error tolerance signal. ### Claim 9 (depends on 2) The circuit of claim 2, wherein the controller is configured to receive a control signal indicative of an input-driven mode or an on-demand mode. ### Claim 10 (depends on 9) The circuit of claim 9, wherein the controller is configured to disable the window comparator in response to the on-demand mode. ### Claim 11 (depends on 9) The circuit of claim 9, wherein, while in the input-driven mode and in response to assertion of the trigger signal from the window comparator, the controller is configured to disable the window comparator and to cause the comparison circuitry to subtract the first digital value from the second digital value. ### Claim 12 (depends on 10) The circuit of claim 10, wherein, while in the on-demand mode, the controller is configured to periodically compare pairs of digital values successively output by the ADC and subtract one digital value of a given pair of digital values from the other digital value of the given pair. ### Claim 13 (depends on 9) The circuit of claim 9, wherein, while in the on-demand mode, the controller is configured to disable the window comparator. ### Claim 14 (depends on 13) The circuit of claim 13, wherein, while in the on-demand mode, the controller is configured to initiate comparison of pairs of digital values successively output by the ADC according to a timer. ### Claim 15 (depends on 1) The circuit of claim 1, wherein the programmable clock circuit comprises: a multiplexer configured to receive first and second values, the second value being one-half of the first value; and a clock divider configured to receive and divide down the clock signal by a value output by the multiplexer. ### Claim 16 (depends on 15) The circuit of claim 15, wherein the controller is configured to cause the multiplexer to select the second value and to cause the comparison circuitry to subtract pairs of digital values. ### Claim 17 A circuit comprising: an analog-to-digital converter (ADC) having selectable first and second analog channel inputs; a window comparator configured to compare a digital value output by the ADC to first and second threshold values defining a window and to assert a trigger signal in response to the digital value being outside the window; a programmable clock circuit configured to provide a clock signal to the ADC; a controller configured to generate, in response to assertion of the trigger signal, a sample rate control signal to cause the programmable clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs; and comparison circuitry configured to compare a first digital output from the ADC to a second digital output from the ADC. ### Claim 18 (depends on 17) The circuit of claim 17, wherein, responsive to assertion of the trigger signal, the controller is configured to disable the window comparator. ### Claim 19 (depends on 17) The circuit of claim 17, wherein the comparison circuitry is configured to determine whether a difference between the first and second digital outputs is greater than a threshold. ### Claim 20 A method, comprising: applying a clock signal having a first frequency to an analog-to-digital converter (ADC); increasing the frequency of the clock signal to a second frequency in response to a first control signal; and comparing a first digital value output by the ADC to a second digital value output by the ADC, the first and second digital values output by the ADC in succession and representing a pair; and asserting a fault signal responsive to a difference between the pair of digital values being greater than a threshold. ### Claim 21 (depends on 20) The method of claim 20, further comprising: enabling a window comparator; and asserting, by the window comparator, the first control signal in response to a digital value output by the ADC being above or below a window set by the window comparator.