# US 12,184,296 B2 · Systems and method of compensating for nonlinear capacitance in converters

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- Number: US 12,184,296 B2
- Document ID: US12184296B2
- Status: Granted
- Kind: B2
- Application number: 17/950,567
- Filed: 2022-09-22
- Published: 2024-03-28
- Granted: 2024-12-31
- Earliest claimed: 2022-09-22
- Assignees: Avago Technologies International Sales Pte. Limited
- Applicants: Avago Technologies International Sales Pte. Limited
- Inventors: Jan Mulder; Frank Van der Goes; Mohammadreza Mehrpoo; Sijia Wang
- Web page: https://patentgrep.com/patent/US12184296B2

## CPC

- H03M 1/0604: {at one point, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18)}
- H03M 1/0863: {of switching transients, e.g. glitches}
- H03F 3/195: in integrated circuits
- H03F 3/245: {with semiconductor devices only}
- H03F 3/45188: {Non-folded cascode stages}
- H03M 1/742: {using current sources as quantisation value generators}
- H03F 2200/451: the amplifier being a radio frequency amplifier
- H03M 1/1014: {at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18)}
- H03M 1/1042: {the look-up table containing corrected values for replacing the original digital values (H03M1/1052 takes precedence)}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H03F: AMPLIFIERS

## Abstract

Described herein are systems and methods related to a converter includes a number of unit cells. The unit cells each include a first transistor and a second transistor. The first transistor is coupled in series with an output of the unit cell, and the second transistor is configured to have a capacitive characteristic that reduces a non-linear capacitive characteristic of the first transistor. The converter can be a voltage or current mode digital to analog converter.

## Claims

### Claim 1

A converter, comprising:
a plurality of unit cells, wherein the unit cells each comprise a first transistor and a second transistor, wherein the first transistor is coupled in series with an output of a unit cell and wherein the second transistor is configured to have a capacitive characteristic that reduces a non-linear capacitive characteristic of the first transistor wherein a gate of the second transistor is coupled to the output and a bias circuit is coupled between a drain of the second transistor and a source of the second transistor.

### Claim 2 (depends on 1)

The converter of claim 1, wherein the unit cells are voltage or current mode digital to analog converter cells.

### Claim 3 (depends on 1)

The converter of claim 1, wherein the first transistor and the second transistor are each N-channel transistors or are each P-channel transistors.

### Claim 4 (depends on 1)

The converter of claim 1, wherein a gate of the second transistor is coupled to the output.

### Claim 5 (depends on 1)

The converter of claim 1, wherein a gate of the second transistor is coupled to the output and a bias circuit is coupled to a drain of the second transistor and source of the second transistor, the drain and the source being coupled together.

### Claim 6 (depends on 1)

The converter of claim 1, wherein a bias circuit is coupled to the second transistor and the bias circuit receives a signal at the output.

### Claim 7 (depends on 1)

The converter of claim 1, wherein the non-linear capacitive characteristic of the first transistor is associated with a parasitic gate drain capacitance.

### Claim 8 (depends on 1)

The converter of claim 1, wherein the unit cells each comprise a third transistor, wherein the third transistor is coupled to another output of the unit cell and wherein the third transistor is configured to have a capacitive characteristic that reduces a non-linear capacitive characteristic of the second transistor.

### Claim 9 (depends on 1)

The converter of claim 1, wherein the first transistor is a cascode transistor.

### Claim 10 (depends on 1)

The converter of claim 1, wherein the unit cells each comprise a third transistor coupled in series with the first transistor, wherein the first transistor and the third transistor are cascode transistors and the first transistor is between the third transistor and the output.

### Claim 11

A converter, comprising:
a plurality of unit cells, wherein the unit cells each comprise a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitive element and a second capacitive element, the first transistor being configured to drive a signal at a first output, the second transistor being configured to drive a signal at a second output, wherein the third transistor is configured to reduce an output swing experienced by the first transistor, wherein the fourth transistor is configured to reduce an output swing experienced by the second transistor, wherein the first capacitive element is configured to have a capacitive characteristic that reduces a non-linear capacitive characteristic of the first transistor, wherein the second capacitive element is configured to have a capacitive characteristic that reduces a non-linear capacitive characteristic of the second transistor.

### Claim 12 (depends on 11)

The converter of claim 11, wherein the unit cells are current mode digital to analog converter cells and wherein the first capacitive element and the second capacitive element are each N-channel transistors or are each P-channel transistors.

### Claim 13 (depends on 12)

The converter of claim 12, wherein a gate of the first capacitive element is coupled to the first output and a first bias circuit is coupled between a drain of the first capacitive element and source of the second capacitive element.

### Claim 14 (depends on 13)

The converter of claim 13, wherein a gate of the second capacitive element is coupled to the second output and a second bias circuit is coupled between a drain of the second capacitive element and a source of the second capacitive element.

### Claim 15 (depends on 14)

The converter of claim 14, wherein the first capacitive element and the second capacitive element are N-channel transistors.

### Claim 16

A method of reducing a nonlinear capacitive response of converter, comprising:
a plurality of unit cells, wherein the unit cells each comprise a first transistor and a second transistor, wherein the first transistor is coupled in series with a first output of a unit cell, wherein the second transistor is coupled in series with a second output of the unit cell, the method comprising:
biasing a first active element so that the first active element has a capacitive characteristic that reduces a non-linear capacitive characteristic of the first transistor; and
biasing a second active element so that the second active element has a capacitive characteristic that reduces a non-linear capacitive characteristic of the second transistor.

### Claim 17 (depends on 16)

The method of claim 16, wherein the first active element is a transistor configured as a capacitor.

### Claim 18 (depends on 16)

The method of claim 16 further comprising:
biasing a third active element so that the third active element has a capacitance characteristic that reduces a non-linear capacitive characteristic of the first active element and the non-linear capacitive characteristic of the first transistor.

### Claim 19 (depends on 16)

The method of claim 16, wherein the first active element is biased using an output signal at the first output.