# US 12,184,292 B2 · Sub-sampling phase locked loop (SSPLL) with saturated reference feedback

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- Number: US 12,184,292 B2
- Document ID: US12184292B2
- Status: Granted
- Kind: B2
- Application number: 18/355,146
- Filed: 2023-07-19
- Published: 2024-01-25
- Granted: 2024-12-31
- Earliest claimed: 2022-07-22
- Assignees: The Regents of the University of Michigan
- Applicants: The Regents of the University of Michigan
- Inventors: Matthew R. Belz; Lu Jie; Seungheun Song; Michael P. Flynn
- Web page: https://patentgrep.com/patent/US12184292B2

## CPC

- H03L 7/091: the phase or frequency detector using a sampling device (H03L7/087 takes precedence)
- H03K 19/1737: {using multiplexers (H03K19/1738 takes precedence)}
- H03L 7/08: Details of the phase-locked loop
- H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A phase locked loop (PLL) includes a phase detector configured to receive a reference signal and a feedback signal, wherein the reference signal has a reference frequency, sample the feedback signal, and output a phase detection signal indicative of a phase of the feedback signal. A voltage controlled oscillator is configured to generate an output signal based on the phase detection signal. The output signal has an output frequency greater than the reference frequency. Feedback circuitry is configured to detect a signal edge of the output signal and selectively supply, once per cycle of the reference signal, the detected signal edge of the output signal as the feedback signal.

## Claims

### Claim 1

A phase locked loop (PLL), comprising:
a phase detector configured to
receive a reference signal and a feedback signal, wherein the reference signal has a reference frequency,
sample the feedback signal, and
output a phase detection signal indicative of a phase of the feedback signal;
a voltage controlled oscillator configured to generate an output signal based on the phase detection signal, wherein the output signal has an output frequency greater than the reference frequency; and
feedback circuitry configured to
detect a signal edge of the output signal, and
selectively supply, once per cycle of the reference signal, the detected signal edge of the output signal as the feedback signal.

### Claim 2 (depends on 1)

The PLL of claim 1, wherein the PLL is a sub-sampling PLL (SSPLL).

### Claim 3 (depends on 1)

The PLL of claim 1, wherein the feedback circuitry includes a multiplexer configured to selectively supply the detected signal edge of the output signal in accordance with a selection signal.

### Claim 4 (depends on 3)

The PLL of claim 3, wherein the multiplexer is configured to supply, in accordance with the selection signal, a supply voltage as the feedback signal when not supplying the detected signal edge.

### Claim 5 (depends on 3)

The PLL of claim 3, wherein the feedback circuitry includes a selection control module configured to detect the signal edge of the output signal and generate the selection signal based on the detected signal edge.

### Claim 6 (depends on 5)

The PLL of claim 5, wherein the selection control module is configured to control a pulse of the selection signal to coincide with the detected signal edge.

### Claim 7 (depends on 6)

The PLL of claim 6, wherein the selection control module controls the pulse of the selection signal to occur only once per cycle of the reference signal.

### Claim 8 (depends on 6)

The PLL of claim 6, wherein the selection control module includes an averaging circuit configured to obtain an average voltage of the output signal in a pulse window determined by the selection control module, and wherein the selection control module is configured to detect the signal edge of the output signal based on the average voltage of the output signal in the pulse window.

### Claim 9 (depends on 8)

The PLL of claim 8, wherein the selection control module is configured to detect the signal edge of the output signal based on a determination of whether the average voltage of the output signal is within a predetermined range of a target voltage.

### Claim 10 (depends on 9)

The PLL of claim 9, wherein the target voltage is a common mode voltage of the output signal.

### Claim 11 (depends on 1)

The PLL of claim 1, wherein the signal edge is a rising edge or a falling edge of the output signal.

### Claim 12 (depends on 1)

The PLL of claim 1, further comprising a charge pump configured to receive phase detection signal and convert the phase detection signal to a control signal.

### Claim 13 (depends on 12)

The PLL of claim 12, further comprising a loop filter configured to output an average of the control signal.

### Claim 14

A sub-sampling phase locked loop (SSPLL), comprising:
a phase detector configured to
receive a reference signal and a feedback signal, wherein the reference signal has a reference frequency,
sample the feedback signal, and
output a phase detection signal indicative of a phase of the feedback signal;
a voltage controlled oscillator configured to generate an output signal based on the phase detection signal, wherein the output signal has an output frequency greater than the reference frequency;
a selection control module configured to detect a signal edge of the output signal and generate a selection signal based on the detected signal edge; and
a multiplexer configured to selectively supply as the feedback signal, based on the selection signal,
in a first portion of a cycle of the reference signal, the output signal of the voltage controlled oscillator, and
in a second portion of the cycle of the reference signal, a supply voltage.

### Claim 15 (depends on 14)

The SSPLL of claim 14, wherein the selection control module is configured to control a pulse of the selection signal to coincide with the detected signal edge.

### Claim 16 (depends on 15)

The SSPLL of claim 15, wherein the selection control module controls the pulse of the selection signal to occur only once per cycle of the reference signal.

### Claim 17 (depends on 15)

The SSPLL of claim 15, wherein the selection control module includes an averaging circuit configured to obtain an average voltage of the output signal in a pulse window determined by the selection control module, and wherein the selection control module is configured to detect the signal edge of the output signal based on the average voltage of the output signal in the pulse window.

### Claim 18 (depends on 17)

The SSPLL of claim 17, wherein the selection control module is configured to detect the signal edge of the output signal based on a determination of whether the average voltage of the output signal is within a predetermined range of a target voltage.

### Claim 19 (depends on 18)

The SSPLL of claim 18, wherein the target voltage is a common mode voltage of the output signal.

### Claim 20 (depends on 14)

The SSPLL of claim 14, wherein the signal edge is a rising edge or a falling edge of the output signal.