# US 12,184,285 B2 · Latch circuit and memory device

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- Number: US 12,184,285 B2
- Document ID: US12184285B2
- Status: Granted
- Kind: B2
- Application number: 18/362,322
- Filed: 2023-07-31
- Published: 2023-11-23
- Granted: 2024-12-31
- Earliest claimed: 2019-12-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.; Tsmc China Company Limited
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.; Tsmc China Company, Limited
- Inventors: XiuLi Yang; Kuan Cheng; He-Zhou Wan; Ching-Wei Wu; Wenchao Hao
- Web page: https://patentgrep.com/patent/US12184285B2

## CPC

- H03K 3/012: Modifications of generator to improve response time or to decrease power consumption
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 7/106: {Data output latches}
- G11C 7/1066: {Output synchronization}
- G11C 7/1087: {Data input latches}
- G11C 7/1093: {Input synchronization}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 8/06: Address interface arrangements, e.g. address buffers
- H03K 3/0372: {of the primary-secondary type}
- G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and an enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal. In response to the corresponding disabling logic level of the latched clock signal, the input latch is configured to hold a logic level of the latched output signal unchanged, regardless of the input signal having one or more logic level switchings, while the enable signal is having the disabling logic level.

## Claims

### Claim 1

A latch circuit, comprising:
a latch clock generator configured to generate a latched clock signal based on a clock signal and a first enable signal; and
an input latch coupled to the latch clock generator to receive the latched clock signal, the input latch configured to generate a latched output signal based on the latched clock signal and an input signal,
wherein, in response to the first enable signal having a first disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal, and
wherein, in response to the corresponding disabling logic level of the latched clock signal, the input latch is configured to hold a logic level of the latched output signal unchanged, regardless of the input signal having one or more logic level switchings, while the first enable signal is having the first disabling logic level.

### Claim 2 (depends on 1)

The latch circuit of claim 1, wherein
in response to the first enable signal having a first enabling logic level different from the first disabling logic level,
the latch clock generator is configured to switch the logic level of the latched clock signal in accordance with the clock signal, and
in response to the switched logic level of the latched clock signal, the input latch is configured to switch the logic level of the latched output signal in accordance with the input signal.

### Claim 3 (depends on 2)

The latch circuit of claim 2, wherein
a voltage of the first disabling logic level of the first enable signal is higher than a voltage of the first enabling logic level of the first enable signal.

### Claim 4 (depends on 1)

The latch circuit of claim 1, further comprising:
an enable latch configured to generate the first enable signal based on the clock signal and a second enable signal,
wherein the latch clock generator is coupled to the enable latch to receive the first enable signal.

### Claim 5 (depends on 1)

The latch circuit of claim 1, further comprising:
an OR gate configured to generate the first enable signal based on second and third enable signals,
wherein the latch clock generator is coupled to the OR gate to receive the first enable signal.

### Claim 6 (depends on 1)

The latch circuit of claim 1, wherein
the latch clock generator comprises a NAND gate configured to generate the latched clock signal based on the clock signal and a signal corresponding to the first enable signal.

### Claim 7 (depends on 1)

The latch circuit of claim 1, wherein
the latch clock generator is configured to generate the latched clock signal based on the clock signal, the first enable signal, and a second enable signal.

### Claim 8 (depends on 7)

The latch circuit of claim 7, wherein
in response to the second enable signal having a second disabling logic level,
the latch clock generator is configured to set the logic level of the latched clock signal to the corresponding disabling logic level.

### Claim 9 (depends on 8)

The latch circuit of claim 8, wherein
in response to the second enable signal having a second enabling logic level different from the second disabling logic level, the latch clock generator is configured to
set the logic level of the latched clock signal to the corresponding disabling logic level, in response to the first enable signal having the first disabling logic level, and
switch the logic level of the latched clock signal in accordance with the clock signal, in response to the first enable signal having a first enabling logic level different from the first disabling logic level.

### Claim 10

A memory device, comprising:
a memory cell; and
a control circuit coupled to control an operation of the memory cell, the control circuit comprising:
a latch clock generator configured to generate a latched clock signal based on a clock signal and an enable signal; and
an input latch coupled to the latch clock generator to receive the latched clock signal, the input latch configured to generate a latched output signal based on the latched clock signal and an input signal,
wherein
the enable signal corresponds to a write enable signal to enable or disable writing to the memory cell,
in response to the enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal, and
in response to the corresponding disabling logic level of the latched clock signal, the input latch is configured to hold a logic level of the latched output signal unchanged, regardless of the input signal having one or more logic level switchings, while the enable signal is having the disabling logic level.

### Claim 11 (depends on 10)

The memory device of claim 10, wherein
the input signal comprises one of
a data signal containing data to be written to the memory cell, or
a bit-write-mask signal to control selective writing to the memory cell.

### Claim 12 (depends on 10)

The memory device of claim 10, wherein
the control circuit further comprises an enable latch configured to
receive the clock signal and the write enable signal, and
generate the enable signal based on the clock signal and the write enable signal, and the latch clock generator is coupled to the enable latch to receive the enable signal.

### Claim 13 (depends on 12)

The memory device of claim 12, wherein
the input signal comprises one of
a data signal containing data to be written to the memory cell, or
a bit-write-mask signal to control selective writing to the memory cell.

### Claim 14 (depends on 12)

The memory device of claim 12, wherein
the enable latch is configured to hold the disabling logic level of the enable signal in a first duration longer than a second duration of a corresponding logic level of the write enable signal.

### Claim 15 (depends on 10)

The memory device of claim 10, wherein
in response to the enable signal having an enabling logic level different from the disabling logic level of the enable signal,
the latch clock generator is configured to switch the logic level of the latched clock signal in accordance with the clock signal, and
in response to the switched logic level of the latched clock signal, the input latch is configured to switch the logic level of the latched output signal in accordance with the input signal.

### Claim 16

A latch circuit, comprising:
a latch clock generator configured to generate a latched clock signal based on a clock signal and a first enable signal;
an input latch coupled to the latch clock generator to receive the latched clock signal, the input latch configured to generate a latched output signal based on the latched clock signal and an input signal; and
an enable latch configured to generate the first enable signal based on the clock signal and a second enable signal,
wherein the latch clock generator is coupled to the enable latch to receive the first enable signal,
wherein, in response to the first enable signal having a first disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal, and
wherein the enable latch is configured to hold the first disabling logic level of the first enable signal in a first duration longer than a second duration of a corresponding second disabling logic level of the second enable signal.

### Claim 17 (depends on 16)

The latch circuit of claim 16, wherein
in response to the corresponding disabling logic level of the latched clock signal, the input latch is configured to hold a logic level of the latched output signal unchanged regardless of the input signal having one or more logic level switchings while the first enable signal is having the first disabling logic level.

### Claim 18 (depends on 16)

The latch circuit of claim 16, wherein
in response to the first enable signal having a first enabling logic level different from the first disabling logic level,
the latch clock generator is configured to switch the logic level of the latched clock signal in accordance with the clock signal, and
in response to the switched logic level of the latched clock signal, the input latch is configured to switch the logic level of the latched output signal in accordance with the input signal.

### Claim 19 (depends on 18)

The latch circuit of claim 18, wherein
a voltage of the first disabling logic level of the first enable signal is higher than a voltage of the first enabling logic level of the first enable signal.

### Claim 20 (depends on 16)

The latch circuit of claim 16, wherein
the second enable signal comprises:
a chip enable signal to enable or disable a memory device having a memory cell controllable by the latch circuit, or
a write enable signal to enable or disable writing to the memory cell.