# US 12,184,283 B2 · Semiconductor device for logic and memory co-optimization

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- Number: US 12,184,283 B2
- Document ID: US12184283B2
- Status: Granted
- Kind: B2
- Application number: 17/654,803
- Filed: 2022-03-14
- Published: 2022-06-30
- Granted: 2024-12-31
- Earliest claimed: 2018-09-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Jhon Jhy Liaw
- Web page: https://patentgrep.com/patent/US12184283B2

## CPC

- H03K 19/1776: for memories
- H10D 84/853: {comprising FinFETs}
- H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence)
- H10B 10/12: {comprising a MOSFET load element}
- H10B 10/18: {Peripheral circuit regions}
- H10B 99/00: Subject matter not provided for in other groups of this subclass
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 89/10: Integrated device layouts
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Structures and methods for the co-optimization of core (logic) devices and SRAM devices include a semiconductor device having a logic portion and a memory portion. In some embodiments, a logic device is disposed within the logic portion. In some cases, the logic device includes a single fin N-type FinFET and a single fin P-type FinFET. In some examples, a static random-access memory (SRAM) device is disposed within the memory portion. The SRAM device includes an N-well region disposed between two P-well regions, where the two P-well regions include an N-type FinFET pass gate (PG) transistor and an N-type FinFET pull-down (PD) transistor, and where the N-well region includes a P-type FinFET pull-up (PU) transistor.

## Claims

### Claim 1

A semiconductor device, comprising:
a CMOS inverter including a first plurality of FinFETs each having a first number of fins; and
a static random-access memory (SRAM) device including a second plurality of FinFETs each having a second number of fins different than the first number of fins;
wherein the CMOS inverter includes a first epitaxial source/drain region having a first source/drain epitaxial width, and wherein the SRAM device includes a second epitaxial source/drain region having a second source/drain epitaxial width greater than the first source/drain epitaxial width.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the second number of fins is less than the first number of fins.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first number of fins is equal to two, and wherein the second number of fins is equal to one.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the SRAM device includes an N-well region disposed between two P-well regions, wherein the two P-well regions include an N-type FinFET pull-down (PD) transistor, and wherein the N-well region includes a P-type FinFET pull-up (PU) transistor.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the second source/drain epitaxial width is greater than the first source/drain epitaxial width by at least 5%.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein a first gate formed over a first N-type FinFET of the first plurality of FinFETs has a first end-cap length ‘E1’, and wherein a second gate formed over a second N-type FinFET of the second plurality of FinFETs has a second end-cap length ‘E2’ greater than the first end-cap length ‘E1’.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the CMOS inverter has a first active region space ‘S1’ between a channel region of an N-type FinFET of the first plurality of FinFETs and a channel region of a fin P-type FinFET of the first plurality of FinFETs, and wherein the SRAM device has a second active region space ‘S2’ between a pull-down (PD)-channel region and a pull-up (PU)-channel region.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the first active region space ‘S1’ is larger than the second active region space ‘S2’ by at least 20%.

### Claim 9 (depends on 6)

The semiconductor device of claim 6, wherein the second end-cap length ‘E2’ is longer than the first end-cap length ‘E1’ by at least 10%.

### Claim 10 (depends on 6)

The semiconductor device of claim 6, wherein an end-cap length ratio E2/E1 is greater than 1.1.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the CMOS inverter includes a first unit cell having a first X-pitch ‘X1’, wherein the SRAM device includes a second unit cell having a second X-pitch ‘X2’, and wherein the first X-pitch ‘X1’ is the same as the second X-pitch ‘X2’.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein a first fin width for the first plurality of FinFETs is less than a second fin width for the second plurality of FinFETs.

### Claim 13

A circuit, comprising:
a logic unit cell including a first fin in a P-type region and second fin in an N-type region, wherein a gate is disposed over the first fin and the second fin, wherein a first source contact and a second source contact are disposed adjacent to, and on a same side of, the gate and provide contact to respective ones of the first fin and the second fin, wherein a first X-pitch ‘X1’ of the logic unit cell is parallel to a first routing direction of the gate, and wherein the first X-pitch ‘X1’ is defined from a left edge of the first source contact to a right edge of the second source contact; and
a memory unit cell including a plurality of fins and a plurality of gates, wherein a second X-pitch ‘X2’ of the memory unit cell is parallel to a second routing direction of the plurality of gates;
wherein the second X-pitch ‘X2’ is equal to the first X-pitch ‘X1’.

### Claim 14 (depends on 13)

The circuit of claim 13, wherein the CMOS inverter includes a first plurality of FinFETs each having a first number of fins, and wherein the memory unit cell includes a second plurality of FinFETs each having a second number of fins different than the first number of fins.

### Claim 15 (depends on 13)

The circuit of claim 13, wherein each memory unit cell includes an N-well region disposed between two P-well regions, wherein the two P-well regions include an N-type FinFET pull-down (PD) transistor, and wherein the N-well region includes a P-type FinFET pull-up (PU) transistor.

### Claim 16 (depends on 13)

The circuit of claim 13, wherein the logic unit cell has a first active region space ‘S1’ between a channel region of the first fin and a channel region of the second fin, wherein an SRAM device of the memory unit cell has a second active region space ‘S2’ between a PD-channel region and a PU-channel region, and wherein the first active region space ‘S1’ is greater than the second active region space ‘S2’.

### Claim 17 (depends on 13)

The circuit of claim 13, wherein the gate disposed over the first fin and the second fin has a first end-cap length ‘E1’, wherein at least one gate of the plurality of gates formed over an N-type FinFET PD transistor of the memory unit cell has a second end-cap length ‘E2’, and wherein the second end-cap length ‘E2’ is greater than the first end-cap length ‘E1’.

### Claim 18 (depends on 13)

The circuit of claim 13, wherein the first fin and the second fin of the logic unit cell have a first fin width, wherein the plurality of fins of the memory unit cell each have a second fin width, and wherein the first fin width is less than the second fin width.

### Claim 19

A semiconductor device, comprising:
a CMOS logic device including a first transistor with a first fin width, the CMOS logic device having a first isolation spacing between a first N+ region and a first N-well (NW) region and between a first P+ region and a first P-well (PW) region; and
a static random-access memory (SRAM) device including a second transistor with a second fin width, the SRAM device having a second isolation spacing between a second N+ region and a second NW region and between a second P+ region and a second PW region;
wherein the first fin width is less than the second fin width, and wherein the first isolation spacing is greater than the second isolation spacing.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein a gate of the first transistor has an end-cap length ‘E1’, and wherein the end-cap length ‘E1’ is at least two times greater than a thickness of a metal gate layer of the gate.