# US 12,184,280 B2 · Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance

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- Number: US 12,184,280 B2
- Document ID: US12184280B2
- Status: Granted
- Kind: B2
- Application number: 18/341,927
- Filed: 2023-06-27
- Published: 2024-01-25
- Granted: 2024-12-31
- Earliest claimed: 2017-10-30
- Applicants: Lodestar Licensing Group, LLC
- Inventors: Dean Gans
- Web page: https://patentgrep.com/patent/US12184280B2

## CPC

- H03K 19/018585: {programmable}
- G06F 13/4086: {Bus impedance matching, e.g. termination}
- G11C 7/02: with means for avoiding parasitic signals
- G11C 29/02: Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C 29/022: {in I/O circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/50008: {of impedance}
- H03K 19/0005: {Modifications of input or output impedance}
- G11C 7/04: with means for avoiding disturbances due to temperature effects
- G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information}
- G11C 2207/2254: Calibration
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance are disclosed. A memory device of a semiconductor device may be set in an identification mode and provide an identification request to other memory devices that are coupled to a common communication channel. The memory devices that are coupled to the common communication channel may share an external resistance, for example, for calibration of respective programmable termination components of the memory devices. The memory devices that receive the identification request set a respective identification flag which can be read to determine which memory devices share an external resistance with the memory device having the set identification mode.

## Claims

### Claim 1

An apparatus comprising:
a dynamic random access memory (DRAM) device configured to be coupled to a shared external resistance for calibration of a termination impedance (ZQ), wherein the DRAM device comprises a mode register configured to store an operand, and wherein a value of the operand is configured to indicate a ZQ Master designation of the DRAM device.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the value of the operand is 0 to indicate that the DRAM device is not a ZQ Master or 1 to indicate that the DRAM device is the ZQ Master.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the operand is operand 6 (OP[6]).

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the DRAM device is configured to perform the calibration of the termination impedance responsive to a command.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the mode register comprises eight (8) bits corresponding to operands 7 through 0 (OP[7:0]).

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the DRAM device is configured to provide the value of the operand responsive to a mode register read command.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the DRAM device is configured to arbitrate among a plurality of DRAM devices for use of the shared external resistance.

### Claim 8

A method comprising:
receiving a mode register read command at a dynamic random access memory device (DRAM) coupled to a shared external resistance; and
providing, responsive to the mode register read command, a value of an operand of a mode register of the DRAM device, wherein the value of the operand indicates a termination impedance (ZQ) Master designation of the DRAM device.

### Claim 9 (depends on 8)

The method of claim 8, wherein the value of the operand is 0 to indicate that the DRAM device is not a ZQ Master or 1 to indicate that the DRAM device is the ZQ Master.

### Claim 10 (depends on 8)

The method of claim 8, wherein the operand is operand 6 (OP[6]).

### Claim 11 (depends on 8)

The method of claim 8, further comprising:
performing, by a calibration circuit of the DRAM device, a ZQ calibration operation responsive to a command.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
arbitrating, by the calibration circuit of the DRAM device and among a plurality of DRAM devices, for use of the shared external resistance to perform the ZQ calibration operation.

### Claim 13 (depends on 8)

The method of claim 8, wherein the mode register comprises eight (8) bits corresponding to operands 7 through 0 (OP[7:0]).

### Claim 14

An apparatus comprising:
a package comprising a plurality of dynamic random access memory (DRAM) dice including a designated DRAM die or dice, wherein the designated DRAM die or dice comprise a mode register configured to store an operand indicating the designated DRAM die.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein the operand is 0 to indicate that a DRAM die of the plurality of DRAM dice is not the designated DRAM die or 1 to indicate that the DRAM die is the designated DRAM die.

### Claim 16 (depends on 14)

The apparatus of claim 14, wherein the operand is operand 6 (OP[6]).

### Claim 17 (depends on 14)

The apparatus of claim 14, wherein the plurality of DRAM dice are configured to perform a calibration of a termination impedance responsive to a command received by the designated DRAM die.

### Claim 18 (depends on 14)

The apparatus of claim 14, wherein the mode register comprises eight (8) bits corresponding to operands 7 through 0 (OP[7:0]).

### Claim 19 (depends on 14)

The apparatus of claim 14, wherein the plurality of DRAM dice are configured to provide the operand responsive to a mode register read command.

### Claim 20 (depends on 14)

The apparatus of claim 14, wherein the designated DRAM die or dice are configured to arbitrate among the plurality of DRAM dice for use of a shared external resistance.