# US 12,184,277 B2 · Synthesis driven for minimum leakage with new standard cells > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,184,277 B2 - Document ID: US12184277B2 - Status: Granted - Kind: B2 - Application number: 18/308,215 - Filed: 2023-04-27 - Published: 2024-10-31 - Granted: 2024-12-31 - Earliest claimed: 2023-04-27 - Assignees: STMicroelectronics International N.V. - Applicants: STMicroelectronics International N.V. - Inventors: Giulia Colonna; Enea Dimroci - Web page: https://patentgrep.com/patent/US12184277B2 ## CPC - H03K 19/0016: {by using a control or a clock signal, e.g. in order to apply power supply} - H03K 19/0013: {in field effect transistor circuits} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract According to an embodiment, an integrated circuit includes a complementary metal-oxide-semiconductor (CMOS) logic gate, a series p-channel transistor, and a shunt n-channel transistor. The CMOS logic gate includes a first p-channel transistor and a first n-channel transistor. The first p-channel transistor and the series p-channel transistor are configurable to be body biased. The series p-channel transistor is coupled between an output terminal of the CMOS logic gate and the first p-channel transistor. The shunt n-channel transistor is coupled between the output terminal of the CMOS logic gate and the reference ground. A gate terminal of the series p-channel transistor is coupled to a gate terminal of the shunt n-channel transistor and configured to receive a sleep signal during a low-power operating mode of the CMOS logic gate. ## Claims ### Claim 1 An integrated circuit, comprising: a complementary metal-oxide-semiconductor (CMOS) logic gate including a first p-channel transistor and a first n-channel transistor, wherein the first p-channel transistor is configurable to be body biased; a series p-channel transistor coupled between an output terminal of the CMOS logic gate and the first p-channel transistor, wherein the series p-channel transistor is configurable to be body biased; and a shunt n-channel transistor coupled between the output terminal of the CMOS logic gate and reference ground, wherein a gate terminal of the series p-channel transistor is coupled to a gate terminal of the shunt n-channel transistor and configured to receive a sleep signal during a low-power operating mode of the CMOS logic gate. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the first p-channel transistor and the series p-channel transistor are coupled in series between a voltage source terminal of the CMOS logic gate and the output terminal of the CMOS logic gate, and wherein the first n-channel transistor and the shunt n-channel transistor are coupled in parallel between the output terminal of the CMOS logic gate and the reference ground. ### Claim 3 (depends on 1) The integrated circuit of claim 1, wherein a body bias voltage is applied to the first p-channel transistor and the series p-channel transistor to body bias the first p-channel transistor and the series p-channel transistor. ### Claim 4 (depends on 1) The integrated circuit of claim 1, wherein the CMOS logic gate includes a second p-channel transistor and a second n-channel transistor, wherein the second p-channel transistor is configurable to be body biased, wherein the first p-channel transistor, the second p-channel transistor, and the series p-channel transistor are arranged in series between a voltage source terminal of the CMOS logic gate and the output terminal of the CMOS logic gate, and wherein the first n-channel transistor, the second n-channel transistor, and the shunt n-channel transistor are coupled in parallel between the output terminal of the CMOS logic gate and the reference ground. ### Claim 5 (depends on 1) The integrated circuit of claim 1, wherein the CMOS logic gate includes a second p-channel transistor and a second n-channel transistor, wherein the second p-channel transistor is configurable to be body biased, wherein the first p-channel transistor and the second p-channel transistor are arranged in parallel between a voltage source terminal of the CMOS logic gate and the series p-channel transistor, and wherein the first n-channel transistor, the second n-channel transistor, and the shunt n-channel transistor are coupled in parallel between the output terminal of the CMOS logic gate and the reference ground. ### Claim 6 (depends on 1) The integrated circuit of claim 1, wherein the CMOS logic gate is a logic NAND gate, a logic NOR gate, a logic NOT gate, or a combination thereof. ### Claim 7 (depends on 1) The integrated circuit of claim 1, further comprising a multiplexer having a first input terminal, a second input terminal, a select terminal, and an output terminal, wherein the first input terminal is coupled to the output terminal of the CMOS logic gate, wherein the second input terminal is couplable to a controller, wherein the select terminal is coupled to the sleep signal, and wherein the multiplexer is configured to: set an output signal at the output terminal of the multiplexer to a signal at the first input terminal in response to the sleep signal being de-asserted; and set an output signal at the output terminal of the multiplexer to a signal at the second input terminal in response to the sleep signal being asserted, wherein the signal at the second input terminal is a desired output value. ### Claim 8 A complementary metal-oxide-semiconductor (CMOS) logic gate, comprising: a first p-channel transistor coupled between a voltage source terminal of the CMOS logic gate and an output terminal of the CMOS logic gate, the first p-channel transistor configured to be body biased; a first n-channel transistor coupled between the output terminal and reference ground; a series p-channel transistor coupled between the output terminal and the first p-channel transistor, wherein the series p-channel transistor is configured to be body biased; and a shunt n-channel transistor coupled between the output terminal and reference ground, wherein a gate terminal of the series p-channel transistor is coupled to a gate terminal of the shunt n-channel transistor and configured to receive a sleep signal during a low-power operating mode of the CMOS logic gate. ### Claim 9 (depends on 8) The CMOS logic gate of claim 8, wherein the first p-channel transistor and the series p-channel transistor are coupled in series between the voltage source terminal and the output terminal, and wherein the first n-channel transistor and the shunt n-channel transistor are coupled in parallel between the output terminal and the reference ground. ### Claim 10 (depends on 8) The CMOS logic gate of claim 8, wherein a body bias voltage is applied to the first p-channel transistor and the series p-channel transistor to body bias the first p-channel transistor and the series p-channel transistor. ### Claim 11 (depends on 8) The CMOS logic gate of claim 8, further comprising a second p-channel transistor and a second n-channel transistor, wherein the second p-channel transistor is configured to be body biased, wherein the first p-channel transistor, the second p-channel transistor, and the series p-channel transistor are arranged in series between the voltage source terminal and the output terminal, and wherein the first n-channel transistor, the second n-channel transistor, and the shunt n-channel transistor are coupled in parallel between the output terminal and the reference ground. ### Claim 12 (depends on 8) The CMOS logic gate of claim 8, further comprising a second p-channel transistor and a second n-channel transistor, wherein the second p-channel transistor is configured to be body biased, wherein the first p-channel transistor and the second p-channel transistor are arranged in parallel between the voltage source terminal and the series p-channel transistor, and wherein the first n-channel transistor, the second n-channel transistor, and the shunt n-channel transistor are coupled in parallel between the output terminal and the reference ground. ### Claim 13 (depends on 8) The CMOS logic gate of claim 8, wherein the CMOS logic gate is a logic NAND gate, a logic NOR gate, a logic NOT gate, or a combination thereof. ### Claim 14 A device, comprising an integrated circuit, the integrated circuit having: a complementary metal-oxide-semiconductor (CMOS) logic gate including a first p-channel transistor and a first n-channel transistor, wherein the first p-channel transistor is configurable to be body biased; a series p-channel transistor coupled between an output terminal of the CMOS logic gate and the first p-channel transistor, wherein the series p-channel transistor is configurable to be body biased; and a shunt n-channel transistor coupled between the output terminal of the CMOS logic gate and reference ground, wherein a gate terminal of the series p-channel transistor is coupled to a gate terminal of the shunt n-channel transistor and configured to receive a sleep signal during a low power operating mode of the CMOS logic gate. ### Claim 15 (depends on 14) The device of claim 14, wherein the first p-channel transistor and the series p-channel transistor are coupled in series between a voltage source terminal of the CMOS logic gate and the output terminal of the CMOS logic gate, and wherein the first n-channel transistor and the shunt n-channel transistor are coupled in parallel between the output terminal of the CMOS logic gate and the reference ground. ### Claim 16 (depends on 14) The device of claim 14, wherein a body bias voltage is applied to the first p-channel transistor and the series p-channel transistor to body bias the first p-channel transistor and the series p-channel transistor. ### Claim 17 (depends on 14) The device of claim 14, wherein the CMOS logic gate includes a second p-channel transistor and a second n-channel transistor, wherein the second p-channel transistor is configurable to be body biased, wherein the first p-channel transistor, the second p-channel transistor, and the series p-channel transistor are arranged in series between a voltage source terminal of the CMOS logic gate and the output terminal of the CMOS logic gate, and wherein the first n-channel transistor, the second n-channel transistor, and the shunt n-channel transistor are coupled in parallel between the output terminal of the CMOS logic gate and the reference ground. ### Claim 18 (depends on 14) The device of claim 14, wherein the CMOS logic gate includes a second p-channel transistor and a second n-channel transistor, wherein the second p-channel transistor is configurable to be body biased, wherein the first p-channel transistor and the second p-channel transistor are arranged in parallel between a voltage source terminal of the CMOS logic gate and the series p-channel transistor, and wherein the first n-channel transistor, the second n-channel transistor, and the shunt n-channel transistor are coupled in parallel between the output terminal of the CMOS logic gate and the reference ground. ### Claim 19 (depends on 14) The device of claim 14, wherein the CMOS logic gate is a logic NAND gate, a logic NOR gate, a logic NOT gate, or a combination thereof. ### Claim 20 (depends on 14) The device of claim 14, wherein the integrated circuit further comprises a multiplexer having a first input terminal, a second input terminal, a select terminal, and an output terminal, wherein the first input terminal is coupled to the output terminal of the CMOS logic gate, wherein the second input terminal is couplable to a controller, wherein the select terminal is coupled to the sleep signal, and wherein the multiplexer is configured to: set an output signal at the output terminal of the multiplexer to a signal at the first input terminal in response to the sleep signal being de-asserted; and set an output signal at the output terminal of the multiplexer to a signal at the second input terminal in response to the sleep signal being asserted, wherein the signal at the second input terminal is a desired output value.