# US 12,184,266 B2 · Electronic package structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,184,266 B2 - Document ID: US12184266B2 - Status: Granted - Kind: B2 - Application number: 18/112,464 - Filed: 2023-02-21 - Published: 2023-06-29 - Granted: 2024-12-31 - Earliest claimed: 2020-02-18 - Assignees: Advanced Semiconductor Engineering, Inc. - Applicants: Advanced Semiconductor Engineering, Inc. - Inventors: Chi Sheng Tseng; Lu-Ming Lai; Ching-Han Huang; Kuo-Hua Lai; Hui-Chung Liu - Web page: https://patentgrep.com/patent/US12184266B2 ## CPC - H03H 9/02102: {of temperature influence (cutting angles H03H9/02015)} - H03H 9/2426: {in combination with other electronic elements} - H03H 3/0073: {Integration with other electronic structures} - H03H 9/02448: {of temperature influence} - H03H 9/0533: {consisting of wire} - H03H 9/0547: {consisting of a vertical arrangement (H03H9/0566 takes precedence)} - H03H 9/08: Holders with means for regulating temperature - H03H 9/1014: {the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the BAW device} - H03H 9/1057: {for microelectro-mechanical devices} - H03L 1/028: {of generators comprising piezoelectric resonators (H03L1/021, H03L1/022 take precedence; oscillation generators with a piezoelectric resonator H03B5/32)} - H03L 1/04: Constructional details for maintaining temperature constant - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 72/879: {Bump connectors and bond wires} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 90/732: {between stacked chips} - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The present disclosure provides a semiconductor package structure. The semiconductor package structure includes a substrate, a first electronic component and a support component. The first electronic component is disposed on the substrate. The first electronic component has a backside surface facing a first surface of the substrate. The support component is disposed between the backside surface of the first electronic component and the first surface of the substrate. The backside surface of the first electronic component has a first portion connected to the support component and a second portion exposed from the support component. ## Claims ### Claim 1 An electronic package structure, comprising: a carrier; a first electronic component disposed adjacent to the carrier, wherein the first electronic component comprises a heat source region configured to maintain a constant temperature of a second electronic component which is disposed over the heat source region, and a backside surface of the second electronic component is thermally connected to the heat source region by a thermal bonding layer; and a wire electrically connecting the first electronic component and the carrier, wherein the wire has a first end and a second end opposite to the first end, and the first end is substantially at a same level with the second end, wherein the second end of the wire is on the carrier and below a top surface of the carrier. ### Claim 2 (depends on 1) The electronic package structure as claimed in claim 1, wherein the heat source region is embedded in the first electronic component and exposed from an active surface of the first electronic component. ### Claim 3 (depends on 2) The electronic package structure as claimed in claim 2, wherein a surface of the heat source region is substantially coplanar with the active surface of the first electronic component. ### Claim 4 (depends on 1) The electronic package structure as claimed in claim 1, wherein a portion of the heat source region is exposed from the thermal bonding layer. ### Claim 5 (depends on 4) The electronic package structure as claimed in claim 4, wherein a width of the second electronic component is less than a width of the heat source region. ### Claim 6 An electronic package structure, comprising a carrier; a first electronic component disposed adjacent to the carrier, wherein the first electronic component comprises a heat source region configured to maintain a constant temperature of a second electronic component which is disposed over the heat source region, and a backside surface of the second electronic component is thermally connected to the heat source region by a thermal bonding layer; and a support component disposed between the first electronic component and the carrier, wherein a projection of the support component on the carrier and a projection of the heat source region on the carrier overlap in a vertical direction. ### Claim 7 (depends on 6) The electronic package structure as claimed in claim 6, wherein a width of the support component is less than a width of the heat source region. ### Claim 8 (depends on 6) The electronic package structure as claimed in claim 6, further comprising a wire electrically connecting the first electronic component and the second electronic component. ### Claim 9 (depends on 8) The electronic package structure as claimed in claim 8, wherein the wire has a first end on the second electronic component, and a projection of the first end is within an area of the heat source region in a vertical direction. ### Claim 10 (depends on 9) The electronic package structure as claimed in claim 9, wherein the wire further has a second end on the first electronic component, and the second end is spaced apart from the heat source region.