# US 12,184,254 B2 · Glitch-free low-pass filter circuit and system circuit using the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,184,254 B2 - Document ID: US12184254B2 - Status: Granted - Kind: B2 - Application number: 18/298,408 - Filed: 2023-04-11 - Published: 2024-02-15 - Granted: 2024-12-31 - Earliest claimed: 2022-08-12 - Assignees: Nuvoton Technology Corporation - Applicants: Nuvoton Technology Corporation - Inventors: Chou-Chuan Chen - Web page: https://patentgrep.com/patent/US12184254B2 ## CPC - H03H 11/04: Frequency selective two-port networks - H03K 5/1252: Suppression or limitation of noise or interference (specially adapted for transmission systems H04B15/00, H04L25/08) - H03K 17/6872: {using complementary field-effect transistors} - H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A glitch-free low-pass filter circuit includes an integrating circuit, a Schmitt trigger, a first feedback logic circuit and a second feedback logic circuit. The integrating circuit is used to integrate an input signal to generate an integral signal. The Schmitt trigger is used to receive the integral signal to generate a hysteresis signal. The first feedback logic circuit is used to pull the integral signal to a reset voltage or up to the set voltage based on an inverted input signal and an inverted hysteresis signal, wherein the inverted input signal and the inverted hysteresis signal are generated by performing an inversion process. The second feedback logic circuit is used to pull the integral signal down to the reset voltage or up to the set voltage based on the inverted hysteresis signal and an output signal, wherein the output signal is generated by performing the inversion process twice. ## Claims ### Claim 1 A glitch-free low-pass filter circuit, comprising: an integrating circuit, configured to receive an input signal of the low-pass filter circuit, and integrate the input signal to generate an integral signal; a Schmitt trigger, electrically connected to the integrating circuit, and configured to receive the integral signal and generate a hysteresis signal based on the integral signal; a first feedback logic circuit, electrically connected to the integrating circuit and the Schmitt trigger, and configured to pull the integral signal down to a reset voltage or up to a set voltage based on an inverted input signal and an inverted hysteresis signal, wherein the inverted input signal is generated by performing an inversion process on the input signal, and the inverted hysteresis signal is generated by performing the inversion process on the hysteresis signal; and a second feedback logic circuit, electrically connected to the Schmitt trigger and the integrating circuit, and configured to pull the integral signal down to the reset voltage or up to the set voltage based on the inverted hysteresis signal and an output signal of the low-pass filter circuit, wherein the output signal is generated by performing the inversion process on the hysteresis signal twice. ### Claim 2 (depends on 1) The glitch-free low-pass filter circuit according to claim 1, wherein the integrating circuit comprising: a first capacitor, wherein one end of the first capacitor is electrically connected to the set voltage; a second capacitor, wherein one end of the second capacitor is electrically connected to the other end of the first capacitor, and the other end of the second capacitor is electrically connected to the reset voltage; and a resistor, wherein one end of the resistor is electrically connected to the other end of the first capacitor, the end of the second capacitor and an input end of the Schmitt trigger, the end of the resistor is configured as an output end of the integrating circuit to output the integral signal, and the other end of the resistor is configured as a receiving end of the integrating circuit to receive the input signal. ### Claim 3 (depends on 1) The glitch-free low-pass filter circuit according to claim 1, further comprising: a first input inverter and a second input inverter, wherein an input end of the first input inverter is configured to receive the input signal, an input end of the second input inverter is electrically connected to an output end of the first input inverter to receive the inverted input signal, and an output end of the second input inverter is configured to output the input signal, on which the inversion process is performed twice, to the integrating circuit. ### Claim 4 (depends on 1) The glitch-free low-pass filter circuit according to claim 1, wherein the first feedback logic circuit comprises: a first logic gate, electrically connected to the Schmitt trigger, and configured to generate a first control signal based on the inverted input signal and the inverted hysteresis signal; a first switch, electrically connected to the set voltage, the integrating circuit and the first logic gate, and configured to pull the integral signal up to the set voltage based on the first control signal; a second logic gate, electrically connected to the Schmitt trigger, and configured to generate a second control signal based on the inverted input signal and the inverted hysteresis signal; and a second switch, electrically connected to the reset voltage, the integrating circuit and the second logic gate, and configured to pull the integral signal down to the reset voltage based on the second control signal. ### Claim 5 (depends on 4) The glitch-free low-pass filter circuit according to claim 4, wherein the first logic gate is an OR gate, the second logic gate is an AND gate, the first switch is a P-type MOS transistor, and the second switch is an N-type MOS transistor. ### Claim 6 (depends on 1) The glitch-free low-pass filter circuit according to claim 1, further comprising: a first output inverter and a second output inverter, wherein an input end of the first output inverter is configured to receive the hysteresis signal, an input end of the second output inverter is electrically connected to an output end of the first output inverter to receive the hysteresis signal, and an output end of the second output inverter is configured to output the hysteresis signal, on which the inversion process is performed twice, as the output signal of the low-pass filter circuit. ### Claim 7 (depends on 1) The glitch-free low-pass filter circuit according to claim 1, wherein the second feedback logic circuit comprises: a third logic gate, electrically connected to the Schmitt trigger, and configured to generate a third control signal based on the inverted hysteresis signal and the output signal; a third switch, electrically connected to the set voltage, the integrating circuit and the third logic gate, and configured to pull the integral signal up to the set voltage based on the third control signal; a fourth logic gate, electrically connected to the Schmitt trigger, and configured to generate a fourth control signal based on the inverted hysteresis signal and the output signal; and a fourth switch, electrically connected to the reset voltage, the integrating circuit and the fourth logic gate, and configured to pull the integral signal down to the reset voltage based on the fourth control signal. ### Claim 8 (depends on 7) The glitch-free low-pass filter circuit according to claim 7, wherein the third logic gate is an OR gate, the fourth logic gate is an AND gate, the third switch is a P-type MOS transistor, and the fourth switch is an N-type MOS transistor. ### Claim 9 A glitch-free low-pass filter circuit, comprising: an integrating circuit, configured to receive an input signal of the low-pass filter circuit, and integrate the input signal to generate an integral signal; a Schmitt trigger, electrically connected to the integrating circuit, and configured to receive the integral signal, and generate a hysteresis signal based on the integral signal; a first feedback logic circuit, electrically connected to the integrating circuit and the Schmitt trigger, and configured to pull the integral signal down to a reset voltage or up to a set voltage based on the input signal and the hysteresis signal; and a second feedback logic circuit, electrically connected to the Schmitt trigger and the integrating circuit, and configured to pull the integral signal down to the reset voltage or up to the set voltage based on a transition state of the hysteresis signal; wherein when the hysteresis signal is transitioned, the second feedback logic circuit pulls the integral signal down to the reset voltage or up to the set voltage regardless of a state of the input signal. ### Claim 10 A system circuit, comprising: a glitch-free low-pass filter circuit, comprising: an integrating circuit, configured to receive an input signal of the low-pass filter circuit, and integrate the input signal to generate an integral signal; a Schmitt trigger, electrically connected to the integrating circuit, and configured to receive the integral signal, and generate a hysteresis signal based on the integral signal; a first feedback logic circuit, electrically connected to the integrating circuit and the Schmitt trigger, and configured to pull the integral signal down to a reset voltage or up to a set voltage based on an inverted input signal and an inverted hysteresis signal, wherein the inverted input signal is generated by performing an inversion process on the input signal, and the inverted hysteresis signal is generated by performing the inversion process on the hysteresis signal; and a second feedback logic circuit, electrically connected to the Schmitt trigger and the integrating circuit, and configured to pull the integral signal down to the reset voltage or up to the set voltage based on the inverted hysteresis signal and an output signal of the low-pass filter circuit, wherein the output signal is generated by performing the inversion process on the hysteresis signal twice; and a load circuit, electrically connected to the low-pass filter circuit, and configured to receive the output signal as a clock signal for operation. ### Claim 11 (depends on 10) The system circuit according to claim 10, wherein the integrating circuit comprising: a first capacitor, wherein one end of the first capacitor is electrically connected to the set voltage; a second capacitor, wherein one end of the second capacitor is electrically connected to the other end of the first capacitor, and the other end of the second capacitor is electrically connected to the reset voltage; and a resistor, wherein one end of the resistor is electrically connected to the other end of the first capacitor, the end of the second capacitor and an input end of the Schmitt trigger, the end of the resistor is configured as an output end of the integrating circuit to output the integral signal, and the other end of the resistor is configured as a receiving end of the integrating circuit to receive the input signal. ### Claim 12 (depends on 10) The system circuit according to claim 10, wherein the low-pass filter circuit further comprises: a first input inverter and a second input inverter, wherein an input end of the first input inverter is configured to receive the input signal, an input end of the second input inverter is electrically connected to an output end of the first input inverter to receive the inverted input signal, and an output end of the second input inverter is configured to output the input signal performed the inversion process twice to the integrating circuit. ### Claim 13 (depends on 10) The system circuit according to claim 10, wherein the first feedback logic circuit comprises: a first logic gate, electrically connected to the Schmitt trigger, and configured to generate a first control signal based on the inverted input signal and the inverted hysteresis signal; a first switch, electrically connected to the set voltage, the integrating circuit and the first logic gate, and configured to pull the integral signal up to the set voltage based on the first control signal; a second logic gate, electrically connected to the Schmitt trigger, and configured to generate a second control signal based on the inverted input signal and the inverted hysteresis signal; and a second switch, electrically connected to the reset voltage, the integrating circuit and the second logic gate, and configured to pull the integral signal down to the reset voltage based on the second control signal. ### Claim 14 (depends on 13) The system circuit according to claim 13, wherein the first logic gate is an OR gate, the second logic gate is an AND gate, the first switch is a P-type MOS transistor, and the second switch is an N-type MOS transistor. ### Claim 15 (depends on 10) The system circuit according to claim 10, wherein the low-pass filter circuit further comprises: a first output inverter and a second output inverter, wherein an input end of the first output inverter is configured to receive the hysteresis signal, an input end of the second output inverter is electrically connected to an output end of the first output inverter to receive the hysteresis signal, and an output end of the second output inverter is configured to output the hysteresis signal performed the inversion process twice as the output signal of the low-pass filter circuit. ### Claim 16 (depends on 10) The system circuit according to claim 10, wherein the second feedback logic circuit comprises: a third logic gate, electrically connected to the Schmitt trigger, and configured to generate a third control signal based on the inverted hysteresis signal and the output signal; a third switch, electrically connected to the set voltage, the integrating circuit and the third logic gate, and configured to pull the integral signal up to the set voltage based on the third control signal; a fourth logic gate, electrically connected to the Schmitt trigger, and configured to generate a fourth control signal based on the inverted hysteresis signal and the output signal; and a fourth switch, electrically connected to the reset voltage, the integrating circuit and the fourth logic gate, and configured to pull the integral signal down to the reset voltage based on the fourth control signal. ### Claim 17 (depends on 16) The system circuit according to claim 16, wherein the third logic gate is an OR gate, the fourth logic gate is an AND gate, the third switch is a P-type MOS transistor, and the fourth switch is an N-type MOS transistor.