Amplitude regulator for crystal oscillator

An electronic device comprising:

• an oscillator circuit portion comprising an inverter having an input terminal and an output terminal, said oscillator circuit portion further comprising a crystal oscillator connected between the input and output terminals of the inverter;
• an amplitude regulator circuit portion arranged to supply a current to the inverter of the oscillator circuit portion, said amplitude regulator being arranged to monitor a voltage at the input terminal of the inverter and to vary the current supplied to said inverter in response to said monitored voltage;
• wherein the amplitude regulator comprises first, second, and third PMOS transistors, and first and second NMOS transistors, said amplitude regulator being arranged such that:
• an input node of the amplitude regulator is connected to the input terminal of the inverter, a respective gate terminal of each of the first and second NMOS transistors, and a respective drain terminal of each of the first NMOS transistor and first PMOS transistor;
• a drain terminal of the second NMOS transistor is connected to a drain terminal of the second PMOS transistor;
• a respective source terminal of each of the first, second, and third PMOS transistors is connected to a positive supply rail;
• a respective source terminal of each of the first and second NMOS transistors is connected to a negative supply rail or ground, wherein the source terminal of the second NMOS transistor is connected to the negative supply rail or ground via a trimming resistor;
• a respective gate terminal of each of the first, second, and third PMOS transistors are connected together and to the respective drain terminals of the second PMOS transistor and second NMOS transistor;
• and
• a drain terminal of the third PMOS transistor is connected to a current input of the inverter of the oscillator circuit portion;
• wherein the amplitude regulator further comprises a back-bias circuit portion arranged to vary a back-bias voltage at a back-gate terminal of the second NMOS transistor, thereby varying a threshold voltage of said second NMOS transistor;
• and
• wherein the threshold voltage of the second NMOS transistor is lower than the threshold voltage of the first NMOS transistor.