# US 12,184,199 B2 · Synchronous bridge rectifier using planar switching elements > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,184,199 B2 - Document ID: US12184199B2 - Status: Granted - Kind: B2 - Application number: 17/858,005 - Filed: 2022-07-05 - Published: 2023-02-23 - Granted: 2024-12-31 - Earliest claimed: 2021-08-17 - Assignees: Champion Microelectronic Corp. - Applicants: Champion Microelectronic Corporation - Inventors: Jeffrey Hwang - Web page: https://patentgrep.com/patent/US12184199B2 ## CPC - H02M 7/219: in a bridge configuration - H02M 1/0083: {Converters characterised by their input or output configuration} - H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters - H02M 7/003: {Constructional details, e.g. physical layout, assembly, wiring or busbar connections} - H02M 7/2195: {the switches being synchronously commutated at the same frequency of the AC input voltage} - H02M 1/0032: {Control circuits allowing low power mode operation, e.g. in standby mode} - H02M 1/38: Means for preventing simultaneous conduction of switches - H02M 1/4225: {using a non-isolated boost converter} - Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS ## Abstract Asynchronous bridge rectifier comprises a monolithic die comprising plurality of planar switching elements, each having a control terminal and two controlled terminals. The bridge rectifier further comprises a plurality of controller integrated circuits mechanically attached to the monolithic die, wherein the controller integrated circuits are configured to sense voltage across the controlled terminals of the planar switching elements and to generate a drive signal at the control terminal of the planar switching elements to control opening and closing of the planar switching elements so as to be capable of rectifying an alternating current input signal to form a rectified direct current output signal. ## Claims ### Claim 1 A bridge rectifier comprising: a monolithic die, the monolithic die comprising: a first planar transistor occupying a first quadrant of the monolithic die; the first planar transistor having a gate, a drain and a source; a second planar transistor occupying a second quadrant of the monolithic die; the second planar transistor having a gate, a drain and a source; a third planar transistor occupying a third quadrant of the monolithic die; the third planar transistor having a gate, a drain and a source; and a fourth planar transistor occupying a fourth quadrant of the monolithic die; the fourth planar transistor having a gate, a drain and a source; a first metallic pad mechanically attached to the monolithic die and occupying portions of the first and second quadrants, the first metallic pad configured to electrically couple the drain of the first planar transistor to the drain of the second planar transistor; a second metallic pad mechanically attached to the monolithic die and occupying portions of the second and third quadrants, the second metallic pad configured to electrically couple the source of the second planar transistor to the drain of the third planar transistor; a third metallic pad mechanically attached to the monolithic die and occupying portions of the third and fourth quadrants, the third metallic pad configured to electrically couple the source of the third planar transistor to the source of the fourth planar transistor; a fourth metallic pad mechanically attached to the monolithic die and occupying portions of the third and fourth quadrants, the fourth metallic pad configured to electrically couple the drain of the fourth planar transistor to the source of the first planar transistor; a fifth metallic pad mechanically attached to the monolithic die and occupying a portion of the first quadrant, the fifth metallic pad coupled to the gate of the first planar transistor; a sixth metallic pad mechanically attached to the monolithic die and occupying a portion of the second quadrant, the sixth metallic pad coupled to the gate of the second planar transistor; a seventh metallic pad mechanically attached to the monolithic die and occupying a portion of the third quadrant, the seventh metallic pad coupled to the gate of the third planar transistor; an eighth metallic pad mechanically attached to the monolithic die and occupying a portions of the fourth quadrant, the eighth metallic pad coupled to the gate of the fourth planar transistor; a plurality of controller integrated circuits mechanically attached to the monolithic die, the plurality of controller integrated circuits configured to generate drive signals for controlling the gate terminals of the first, second, third and fourth planar transistors, wherein the plurality of controller integrated circuits comprises exactly three controller integrated circuits, including a first controller integrated circuit for controlling the gate of the first planar transistor, a second controller integrated circuit for controlling the gate of the second planar transistor, and a third controller integrated circuit for controlling the gate of the third planar transistor and the gate of the fourth planar transistor, wherein the integrated circuit assembly comprises exactly seven terminals, including two bridge rectifier input terminals, two bridge rectifier output terminals, and three supply terminals, one for each of the three integrated circuit controllers; and three capacitors wherein each of the three supply terminals is coupled to corresponding one of the three capacitors and wherein the capacitors are internal to the integrated circuit assembly. ### Claim 2 (depends on 1) The monolithic die according to claim 1, wherein the first, second, third and fourth planar transistors comprise high-electron-mobility transistors (HEMTs). ### Claim 3 (depends on 1) The monolithic die according to claim 1, wherein the first, second, third and fourth planar transistors comprise gallium nitride (GaN) transistors. ### Claim 4 (depends on 1) The monolithic die according to claim 1, wherein the first, second, third and fourth planar transistors comprise materials selected from the group consisting of silicon carbide, bipolar and germanium semiconductor materials. ### Claim 5 A bridge rectifier comprising: a monolithic die, the monolithic die comprising: a first planar transistor occupying a first quadrant of the monolithic die; the first planar transistor having a gate, a drain and a source; a second planar transistor occupying a second quadrant of the monolithic die; the second planar transistor having a gate, a drain and a source; a third planar transistor occupying a third quadrant of the monolithic die; the third planar transistor having a gate, a drain and a source; a fourth planar transistor occupying a fourth quadrant of the monolithic die; the fourth planar transistor having a gate, a drain and a source; a first metallic pad mechanically attached to the monolithic die and occupying portions of the first and second quadrants, the first metallic pad configured to electrically couple the drain of the first planar transistor to the drain of the second planar transistor; a second metallic pad mechanically attached to the monolithic die and occupying portions of the second and third quadrants, the second metallic pad configured to electrically couple the source of the second planar transistor to the drain of the third planar transistor; a third metallic pad mechanically attached to the monolithic die and occupying portions of the third and fourth quadrants, the third metallic pad configured to electrically couple the source of the third planar transistor to the source of the fourth planar transistor; a fourth metallic pad mechanically attached to the monolithic die and occupying portions of the third and fourth quadrants, the fourth metallic pad configured to electrically couple the drain of the fourth planar transistor to the source of the first planar transistor; a fifth metallic pad mechanically attached to the monolithic die and occupying a portion of the first quadrant, the fifth metallic pad coupled to the gate of the first planar transistor; a sixth metallic pad mechanically attached to the monolithic die and occupying a portion of the second quadrant, the sixth metallic pad coupled to the gate of the second planar transistor; a seventh metallic pad mechanically attached to the monolithic die and occupying a portion of the third quadrant, the seventh metallic pad coupled to the gate of the third planar transistor; an eighth metallic pad mechanically attached to the monolithic die and occupying a portions of the fourth quadrant, the eighth metallic pad coupled to the gate of the fourth planar transistor; a plurality of controller integrated circuits mechanically attached to the monolithic die, the plurality of controller integrated circuits configured to generate drive signals for controlling the gate terminals of the first, second, third and fourth planar transistors, wherein the plurality of controller integrated circuits comprises exactly three controller integrated circuits, including a first controller integrated circuit for controlling the gate of the first planar transistor, a second controller integrated circuit for controlling the gate of the second planar transistor, and a third controller integrated circuit for controlling the gate of the third planar transistor and the gate of the fourth planar transistor, wherein the integrated circuit assembly comprises exactly seven terminals, including two bridge rectifier input terminals, two bridge rectifier output terminals, and three supply terminals, one for each of the three integrated circuit controllers; and three capacitors wherein each of the three supply terminals is coupled to corresponding one of the three capacitors and wherein the capacitors are external to the integrated circuit assembly. ### Claim 6 (depends on 5) The monolithic die according to claim 5, wherein the first, second, third and fourth planar transistors comprise high-electron-mobility transistors HEMTs). ### Claim 7 (depends on 5) The monolithic die according to claim 5, wherein the first, second, third and fourth planar transistors comprise gallium nitride (GaN) transistors. ### Claim 8 (depends on 5) The monolithic die according to claim 5, wherein the first, second, third and fourth planar transistors comprise materials selected from the group consisting of silicon carbide, bipolar and germanium semiconductor materials. ### Claim 9 An integrated circuit assembly comprising: a monolithic die comprising: a first planar transistor occupying a first quadrant of the monolithic die, the first planar transistor having a gate, a drain and a source; a second planar transistor occupying a second quadrant of the monolithic die; the second planar transistor having a gate, a drain and a source; a third planar transistor occupying a third quadrant of the monolithic die, the third planar transistor having a gate, a drain and a source; and a fourth planar transistor occupying a fourth quadrant of the monolithic die, the fourth planar transistor having a gate, a drain and a source; a plurality of controller integrated circuits mechanically attached to the monolithic die, the plurality of controller integrated circuits configured to generate drive signals for controlling the gate terminals of the first, second, third and fourth planar transistors, wherein the plurality of controller integrated circuits comprises exactly three controller integrated circuits, including a first controller integrated circuit for controlling the gate of the first planar transistor, a second controller integrated circuit for controlling the gate of the second planar transistor, and a third controller integrated circuit for controlling the gate of the third planar transistor and the gate of the fourth planar transistor, wherein the integrated circuit assembly functions as a bridge rectifier and comprises exactly seven terminals, including two bridge rectifier input terminals, two bridge rectifier output terminals, and three supply terminals, one for each of the three integrated circuit controllers; and three capacitors wherein each of the three supply terminals is coupled to corresponding one of the three capacitors and wherein the capacitors are internal to the integrated circuit assembly. ### Claim 10 (depends on 9) The integrated circuit assembly according to claim 9, wherein each controller integrated circuit comprises a power supply for providing operating power to the corresponding controller integrated circuit, the power supply generating a supply voltage of approximately 12 to 15 volts DC and wherein each controller integrated circuit comprises a gate driver circuitry configured to generate drive signals for controlling the gate terminals of the first, second, third and fourth planar transistors wherein the gate drive signals are each limited to approximately 5.5 volts DC. ### Claim 11 (depends on 9) The integrated circuit assembly according to claim 9, wherein the first, second, third and fourth planar transistors comprise high-electron-mobility transistors (HEMTs). ### Claim 12 (depends on 9) The integrated circuit assembly according to claim 9, wherein the first, second, third and fourth planar transistors comprise gallium nitride (GaN) transistors. ### Claim 13 (depends on 9) The integrated circuit assembly according to claim 9, wherein the first, second, third and fourth planar transistors comprise materials selected from the group consisting of silicon carbide, bipolar and germanium semiconductor materials. ### Claim 14 An integrated circuit assembly comprising: a monolithic die comprising: a first planar transistor occupying a first quadrant of the monolithic die, the first planar transistor having a gate, a drain and a source; a second planar transistor occupying a second quadrant of the monolithic die; the second planar transistor having a gate, a drain and a source; a third planar transistor occupying a third quadrant of the monolithic die, the third planar transistor having a gate, a drain and a source; a fourth planar transistor occupying a fourth quadrant of the monolithic die, the fourth planar transistor having a gate, a drain and a source; a plurality of controller integrated circuits mechanically attached to the monolithic die, the plurality of controller integrated circuits configured to generate drive signals for controlling the gate terminals of the first, second, third and fourth planar transistors, wherein the plurality of controller integrated circuits comprises exactly three controller integrated circuits, including a first controller integrated circuit for controlling the gate of the first planar transistor, a second controller integrated circuit for controlling the gate of the second planar transistor, and a third controller integrated circuit for controlling the gate of the third planar transistor and the gate of the fourth planar transistor, wherein the integrated circuit assembly functions as a bridge rectifier and comprises exactly seven terminals, including two bridge rectifier input terminals, two bridge rectifier output terminals, and three supply terminals, one for each of the three integrated circuit controllers; and three capacitors wherein each of the three supply terminals is coupled to corresponding one of the three capacitors and wherein the capacitors are internal to the integrated circuit assembly. ### Claim 15 (depends on 14) The synchronous bridge rectifier according to claim 14, wherein each controller integrated circuit comprises a power supply for providing operating power to the corresponding controller integrated circuit, the power supply generating a supply voltage of approximately 12 to 15 volts DC and wherein each controller integrated circuit comprises a gate driver circuitry configured to generate drive signals for controlling the gate terminals of the first, second, third and fourth planar transistors wherein the gate drive signals are each limited to approximately 5.5 volts DC. ### Claim 16 (depends on 14) The synchronous bridge rectifier according to claim 14, wherein the first, second, third and fourth planar switching elements comprise high-electron-mobility transistors (HEMTs). ### Claim 17 (depends on 14) The synchronous bridge rectifier according to claim 14, wherein the first, second, third and fourth planar switching elements comprise gallium nitride (GaN) transistors. ### Claim 18 (depends on 14) The synchronous bridge rectifier according to claim 14, wherein the first, second, third and fourth planar switching elements comprise materials selected from the group consisting of silicon carbide, bipolar and germanium semiconductor materials.