# US 12,184,196 B2 · Voltage converter with thyristor gate controlled to conduct a reverse current > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,184,196 B2 - Document ID: US12184196B2 - Status: Granted - Kind: B2 - Application number: 17/903,214 - Filed: 2022-09-06 - Published: 2023-03-09 - Granted: 2024-12-31 - Earliest claimed: 2021-09-08 - Assignees: STMicroelectronics (Tours) SAS - Applicants: STMicroelectronics (Tours) SAS - Inventors: Yannick Hague; Romain Launois - Web page: https://patentgrep.com/patent/US12184196B2 ## CPC - H02M 7/1623: {with control circuit} - H02M 7/5388: with asymmetrical configuration of switches - H02M 1/08: Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters - H02M 7/219: in a bridge configuration - H02M 7/757: using semiconductor devices only - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) ## Abstract A converter includes first and second transistors coupled between first and second nodes, and first and second thyristors coupled between the first and second nodes. The converter is controlled for operation to: in first periods, turn the first transistor and second thyristor on and turn the second transistor and the first thyristor off, and in second periods, turn the first transistor and the second thyristor off and turn the second transistor and the first thyristor on. Further control of converter operation includes, for a third period following each first period, turning the first and second transistors off, turning the second thyristor off, and injecting a current into the gate of the first thyristor. Additional control of converter operation includes, for a fourth period following each second period, turning the first and second transistors off, turning the first thyristor off, and injecting a current into the gate of the second thyristor. ## Claims ### Claim 1 A voltage converter, comprising: a first transistor and a second transistor series-coupled at a first input node between a first output node and a second output node; a first thyristor and a second thyristor series-coupled at a second input node between the first output node and the second output node; wherein an input voltage is received at the first and second input nodes; wherein the voltage converter is controlled so that: during a first period of time, the first transistor and the second thyristor are on and the second transistor and the first thyristor are off; during a second period of time, the first transistor and the second thyristor are off and the second transistor and the first thyristor are on; during a third period of time following each first period of time where a voltage across the first thyristor is negative, the first and second transistors are off, and the second thyristor is off, a current is injected into a gate of the first thyristor to cause the first thyristor to conduct a reverse current flow from cathode to anode of the first thyristor; and during a fourth period of time following each second period of time where a voltage across the second thyristor is negative, the first and second transistors are off, and the first thyristor is off, a current is injected into a gate of the second thyristor to cause the second thyristor to conduct a reverse current flow from cathode to anode of the second thyristor. ### Claim 2 (depends on 1) The converter according to claim 1, wherein the current injected into the gate of the first thyristor in the third period of time is in a range from 20 mA to 200 mA, and wherein the current injected into the gate of the second thyristor in the fourth period of time is in a range from 20 mA to 200 mA. ### Claim 3 (depends on 1) The converter according to claim 1, wherein a cathode of the first thyristor is coupled to the first output node and an anode of the first thyristor is coupled to the second input node and wherein a cathode of the second thyristor is coupled to the second input node and an anode of the second thyristor is coupled to the second output node. ### Claim 4 (depends on 3) The converter according to claim 3, wherein one conduction terminal of the first transistor is coupled to the first output node, another conduction terminal of the first transistor is coupled to the first input node, one conduction terminal of the second transistor is coupled to the first input node, and another conduction terminal of the second transistor is coupled to the second output node. ### Claim 5 (depends on 4) The converter according to claim 4, further comprising an inductor coupled between the first input node and a first supply node and where the second input node is connected to a second supply node. ### Claim 6 (depends on 5) The converter according to claim 5, wherein the input voltage is an AC voltage applied between the first and second supply nodes. ### Claim 7 (depends on 6) The converter according to claim 6, wherein the converter is configured so that a DC voltage is output between the first and second output nodes. ### Claim 8 (depends on 7) The converter according to claim 7, further comprising a capacitor coupled between the first and second nodes. ### Claim 9 (depends on 1) The converter according to claim 1, further comprising a third thyristor and a fourth thyristors series-coupled at the second input between the first output node and the second output node. ### Claim 10 (depends on 9) The converter according to claim 9, wherein a cathode of the third thyristor is coupled to the second input node and an anode of the third thyristor is coupled to the first output node and wherein a cathode of the fourth thyristor is coupled to the second output node and an anode of the fourth thyristor is coupled to the second input node. ### Claim 11 (depends on 10) The converter according to claim 10, wherein the voltage converter is controlled so that: during a fifth period of time, the second transistor and the third thyristor are on, and the first transistor and the first, second, and fourth thyristors are off; and during a sixth period of time, the first transistor and the fourth thyristor are on, and the second transistor and the first, second, and third thyristors are off. ### Claim 12 (depends on 11) The converter according to claim 11, wherein each fifth period of time is followed by the fourth period of time and each sixth period of time is followed by the third period of time. ### Claim 13 (depends on 12) The converter according to claim 12, wherein one conduction terminal of the first transistor is coupled to the first output node, another conduction terminal of the first transistor is coupled to the first input node, one conduction terminal of the second transistor is coupled to the first input node, and another conduction terminal of the second transistor is coupled to the second output node. ### Claim 14 (depends on 13) The converter according to claim 13, further comprising an inductor coupled between the first input node and a first supply node and where the second input node is connected to a second supply node. ### Claim 15 (depends on 14) The converter according to claim 14, wherein the input voltage is an AC voltage applied between the first and second supply nodes. ### Claim 16 (depends on 15) The converter according to claim 15, wherein the converter is configured so that a DC voltage is output between the first and second output nodes. ### Claim 17 (depends on 16) The converter according to claim 16, further comprising a capacitor coupled between the first and second nodes. ### Claim 18 (depends on 1) The converter according to claim 1, wherein the first and second transistors are MOSFET transistors. ### Claim 19 A method of controlling a voltage converter that includes a first transistor and a second transistor series-coupled at a first input node between a first output node and a second output node, and a first thyristor and a second thyristor series-coupled at a second input node between the first output node and the second output node, the method comprising: during a first period of time, turning on the first transistor and the second thyristor and turning off the second transistor and the first thyristor; during a second period of time, turning off the first transistor and the second thyristor and turning on the second transistor and the first thyristor; during a third period of time following each first period of time where a voltage across the first thyristor is negative, turning off the first transistor and second transistor, turning off the second thyristor, and injecting a current into a gate of the first thyristor to cause the first thyristor to conduct a reverse current flow from cathode to anode of the first thyristor; and during a fourth period of time following each second period of time where a voltage across the second thyristor is negative, turning off the first transistor and second transistor, turning off the first thyristor, and injecting a current into a gate of the second thyristor to cause the second thyristor to conduct a reverse current flow from cathode to anode of the second thyristor. ### Claim 20 (depends on 19) The method according to claim 19, wherein the current injected into the gate of the first thyristor in the third period of time is in a range from 20 mA to 200 mA, and wherein the current injected into the gate of the second thyristor in the fourth period of time is in a range from 20 mA to 200 mA. ### Claim 21 (depends on 19) The method according to claim 19, wherein the converter includes a third thyristor and a fourth thyristor series-coupled at the second input between the first output node and the second output node, the method further comprising: during a fifth period of time that is followed by the fourth period of time, turning on the second transistor and the third thyristor, turning off the first transistor and turning on the first, second, and fourth thyristors; and during a sixth period of time that is followed by the third period of time, turning on the first transistor and the fourth thyristor, turning off the second transistor and turning off the first, second, and third thyristors.