# US 12,184,165 B2 · Power factor correction circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,184,165 B2 - Document ID: US12184165B2 - Status: Granted - Kind: B2 - Application number: 17/973,838 - Filed: 2022-10-26 - Published: 2023-09-21 - Granted: 2024-12-31 - Earliest claimed: 2022-03-18 - Assignees: Magnachip Mixed-Signal, Ltd. - Applicants: Magnachip Mixed-Signal, Ltd. - Inventors: Zhiyuan Cui; Jonghyun Kim; Byungki Kim; Tianzhao Gao; Chunyan Zhang; Quan Liu - Web page: https://patentgrep.com/patent/US12184165B2 ## CPC - H02M 1/4208: {Arrangements for improving power factor of AC input} - H02M 1/4225: {using a non-isolated boost converter} - H02M 1/0025: {Arrangements for modifying reference values, feedback values or error values in the control loop of a converter} - H02M 1/32: Means for protecting converters other than automatic disconnection - Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS ## Abstract A power factor correction circuit includes an inductor configured to receive an input voltage and supply an output voltage; a power switch connected to the inductor and configured to control an input current flowing through the inductor; and a switch controller configured to receive a feedback voltage including information on the output voltage and an auxiliary voltage including information on a voltage of the inductor and control an on/off operation of the power switch. The switch controller is further configured to operate in a first mode when the feedback voltage is less than a reference voltage, and operate in a second mode when the feedback voltage is greater than the reference voltage. ## Claims ### Claim 1 A power factor correction circuit comprising: an inductor configured to receive an input voltage and supply an output voltage; a power switch connected to the inductor and configured to control an input current flowing through the inductor; and a switch controller configured to receive a feedback voltage including information on the output voltage and an auxiliary voltage including information on a voltage of the inductor and control an on/off operation of the power switch, wherein the switch controller is further configured to: operate in a first mode when the feedback voltage is less than a reference voltage, operate in a second mode when the feedback voltage is greater than the reference voltage, increase an on-time of the power switch as the feedback voltage approaches a target voltage of the output voltage in the first mode, and maintain the on-time of the power switch constant in the second mode. ### Claim 2 (depends on 1) The power factor correction circuit of claim 1, wherein the switch controller comprises: an error amplifier configured to amplify a difference between the feedback voltage and the target voltage and output an error amplifying signal; a ramp signal generator configured to generate a ramp signal having a different slope according to the feedback voltage and the target voltage of the output voltage while the power switch is turned on; and a pulse width modulation (PWM) controller configured to generate a gate control signal for controlling a switching operation of the power switch by using the auxiliary voltage, the error amplifying signal, and the ramp signal. ### Claim 3 (depends on 2) The power factor correction circuit of claim 2, wherein the ramp signal generator is configured to: generate the ramp signal by supplying currents supplied by a first current source and a second current source to a capacitive element, in the first mode, and generate the ramp signal by supplying a current supplied by the second current source to the capacitive element, in the second mode. ### Claim 4 (depends on 2) The power factor correction circuit of claim 2, wherein the PWM controller comprises: a second comparator configured to generate a second comparison signal by comparing the error amplifying signal and the ramp signal; a zero-crossing detector configured to compare the auxiliary voltage with a predetermined zero-crossing reference voltage and generate a zero-crossing detection signal for turning on the power switch according to a comparison result; and a second latch configured to receive the second comparison signal as a reset input and the zero-crossing detection signal as a set input and output the gate control signal. ### Claim 5 (depends on 3) The power factor correction circuit of claim 3, wherein the ramp signal generator further comprises a second switch connected in parallel with the capacitive element, and wherein the second switch is controlled based on an inverted signal of the gate control signal output by the PWM controller. ### Claim 6 (depends on 3) The power factor correction circuit of claim 3, wherein a magnitude of a current supplied by the first current source is proportional to a difference value between the feedback voltage and the target voltage. ### Claim 7 (depends on 3) The power factor correction circuit of claim 3, wherein the ramp signal generator further comprises a first switch configured to connect the first current source and the capacitive element, and wherein the first switch is controlled based on the feedback voltage and the reference voltage. ### Claim 8 (depends on 7) The power factor correction circuit of claim 7, wherein the ramp signal generator further comprises: a first comparator configured to generate a first comparison signal by comparing the feedback voltage and the reference voltage; and a first latch configured to receive the first comparison signal as a reset input and an initialization pulse as a set input and output a first control signal for controlling the first switch. ### Claim 9 (depends on 1) The power factor correction circuit of claim 1, further comprising another inductor coupled to the inductor, wherein the auxiliary voltage is a voltage of the another inductor with a predetermined turns ratio with respect to the inductor. ### Claim 10 A power factor correction circuit comprising: an inductor configured to receive an input voltage and supply an output voltage; a power switch connected to the inductor and configured to control an input current flowing through the inductor; and a switch controller configured to receive a feedback voltage including information on the output voltage and an auxiliary voltage including information on a voltage of the inductor and control an on/off operation of the power switch, wherein the switch controller is further configured to: generate a gate control signal which varies an on-time of the power switch according to a level of the feedback voltage during an initial operation period, increase the on-time of the power switch as the feedback voltage approaches a target voltage of the output voltage in a first mode, and maintain the on-time of the power switch constant in a second mode. ### Claim 11 (depends on 10) The power factor correction circuit of claim 10, wherein the switch controller comprises: an error amplifier configured to amplify a difference between the feedback voltage and the target voltage and output an error amplifying signal; a ramp signal generator configured to generate a ramp signal having a different slope according to the feedback voltage and the target voltage of the output voltage while the power switch is turned on; and a pulse width modulation (PWM) controller configured to generate a gate control signal for controlling a switching operation of the power switch by using the auxiliary voltage, the error amplifying signal, and the ramp signal. ### Claim 12 (depends on 11) The power factor correction circuit of claim 11, wherein the ramp signal generator is configured to: generate the ramp signal by supplying currents supplied by a first current source and a second current source to a capacitive element, in the first mode, and generate the ramp signal by supplying a current supplied by the second current source to the capacitive element, in the second mode. ### Claim 13 (depends on 12) The power factor correction circuit of claim 12, wherein the PWM controller comprises: a second comparator configured to generate a second comparison signal by comparing the error amplifying signal and the ramp signal; a zero-crossing detector configured to compare the auxiliary voltage with a predetermined zero-crossing reference voltage and generate a zero-crossing detection signal for turning on the power switch according to a comparison result; and a second latch configured to receive the second comparison signal as a reset input and the zero-crossing detection signal as a set input, and output the gate control signal. ### Claim 14 (depends on 12) The power factor correction circuit of claim 12, wherein the ramp signal generator further comprises a second switch connected in parallel with the capacitive element, and wherein the second switch is controlled based on an inverted signal of the gate control signal output by the PWM controller. ### Claim 15 (depends on 12) The power factor correction circuit of claim 12, wherein a magnitude of a current supplied by the first current source is proportional to a difference value between the feedback voltage and the target voltage. ### Claim 16 (depends on 13) The power factor correction circuit of claim 13, wherein the ramp signal generator further comprises a first switch configured to connect the first current source and the capacitive element, and wherein the first switch is controlled based on the feedback voltage and the reference voltage. ### Claim 17 (depends on 16) The power factor correction circuit of claim 16, wherein the ramp signal generator further comprises: a first comparator configured to generate a first comparison signal by comparing the feedback voltage and the reference voltage, and a first latch configured to receive the first comparison signal as a reset input and an initialization pulse as a set input, and output a first control signal for controlling the first switch. ### Claim 18 (depends on 10) The power factor correction circuit of claim 10, further comprising another inductor coupled to the inductor, wherein the auxiliary voltage is a voltage of the another inductor with a predetermined turns ratio with respect to the inductor.