# US 12,183,834 B2 · Cool electron erasing in thin-film storage transistors

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- Number: US 12,183,834 B2
- Document ID: US12183834B2
- Status: Granted
- Kind: B2
- Application number: 18/046,433
- Filed: 2022-10-13
- Published: 2023-03-02
- Granted: 2024-12-31
- Earliest claimed: 2020-01-22
- Assignees: Sunrise Memory Corporation
- Applicants: Sunrise Memory Corporation
- Inventors: Sayeef Salahuddin; George Samachisa; Wu-Yi Henry Chien; Eli Harari
- Web page: https://patentgrep.com/patent/US12183834B2

## CPC

- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 64/037: {comprising charge-trapping insulators}
- G11C 16/10: Programming or data input circuits
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- H10B 43/30: characterised by the memory core region
- H10D 30/694: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer has a value between −1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.

## Claims

### Claim 1

A storage transistor, comprising: a channel region, a gate electrode, a tunnel dielectric layer, a data storage layer, and a barrier layer, wherein (i) the tunnel dielectric layer, the data storage layer, and the barrier layer are provided between the channel region and the gate electrode, (ii) the data storage layer has a conduction band offset that is less than a change in energy level over a thickness of the tunnel dielectric layer, when a programming voltage is applied between the gate electrode and the channel region, such that electrons direct tunnel into the data storage layer; and (iii) the barrier layer has a conduction band offset less than the conduction band offset of the data storage layer.

### Claim 2 (depends on 1)

The storage transistor of claim 1, wherein the data storage layer comprises a charge-trapping layer.

### Claim 3 (depends on 1)

The storage transistor of claim 1, wherein the barrier layer is provided between the tunnel dielectric layer and the data storage layer.

### Claim 4 (depends on 1)

The storage transistor of claim 1, wherein the conduction band offset of the data storage layer is between −1.0 eV and 2.3 eV.

### Claim 5 (depends on 1)

The storage transistor of claim 1, wherein the data storage layer comprises a material selected from the group consisting of: hafnium oxide (HfO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), lanthanum oxide (La2O3) tantalum oxide (Ta2O5), cerium oxide (CeO2), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), silicon nanodots, ruthenium nanodots, platinum nanodots and cobalt nanodots.

### Claim 6 (depends on 1)

The storage transistor of claim 1, wherein the conduction band offset of the data storage layer is greater than the energy difference between a data storage site in the data storage layer and an edge of the conduction band of the data storage layer.

### Claim 7 (depends on 1)

The storage transistor of claim 1, wherein the electrons that direct tunnel into the data storage layer provide a current exceeding 1.0 amps/cm2.

### Claim 8 (depends on 1)

The storage transistor of claim 1, wherein the tunnel dielectric layer has a thickness that allows programming and erasing operations to be accomplished predominantly by direct tunneling.

### Claim 9 (depends on 1)

The storage transistor of claim 1, wherein the tunnel dielectric layer comprises one or more of: silicon oxide, silicon nitride and silicon oxynitride.

### Claim 10 (depends on 1)

The storage transistor of claim 1, wherein the tunnel dielectric layer comprises stoichiometric silicon nitride.

### Claim 11 (depends on 9)

The storage transistor of claim 9, wherein the tunnel dielectric layer comprises silicon oxide that is formed using an ozone step.

### Claim 12 (depends on 11)

The storage transistor of claim 11, wherein the tunnel dielectric layer is formed using a pulsed ozone step, an H2 anneal, a NH3 anneal, a rapid thermal anneal, or any combination thereof.

### Claim 13 (depends on 11)

The storage transistor of claim 11, further comprising in the tunnel dielectric layer a layer of aluminum oxide.

### Claim 14 (depends on 13)

The storage transistor of claim 13, wherein the aluminum oxide layer has a thickness that is not greater than 1 nm.

### Claim 15 (depends on 1)

The storage transistor of claim 1 wherein, when a voltage substantially less than the programming voltage is applied across the channel region and the gate electrode, electrons tunnel into the data storage layer by Fowler-Nordheim tunneling or a modified Fowler-Nordheim tunneling.

### Claim 16 (depends on 15)

The storage transistor of claim 15, wherein the applied voltage corresponds to a programming inhibit voltage or an erase inhibit voltage and wherein electrons tunneling into the data storage layer provides a current density less than 0.1 amps/cm2.

### Claim 17 (depends on 1)

The storage transistor of claim 1, having an average endurance exceeding 1011 programming-erase cycles.

### Claim 18 (depends on 1)

The storage transistor of claim 1, wherein the barrier layer comprises a material having a conduction band offset between −1.00 eV and 1.5 eV.

### Claim 19 (depends on 16)

The storage transistor of claim 16, wherein the barrier layer comprises a material selected from the group consisting of: hafnium oxide (HfO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), tantalum oxide (Ta2O5), cerium oxide (CeO2), titanium oxide (TiO2), silicon-rich silicon nitride (SiN:Si), strontium titanium oxide (SrTiO3), silicon nanodots, ruthenium nanodots, platinum nanodots and cobalt nanodots.

### Claim 20 (depends on 16)

The storage transistor of claim 16, wherein the tunnel dielectric layer comprises silicon oxide, the barrier layer comprises tantalum oxide, and the data storage layer comprises silicon-rich silicon nitride.

### Claim 21 (depends on 16)

The storage transistor of claim 16, wherein the tunnel dielectric layer comprises silicon oxide, the barrier layer comprises cerium oxide, and the data storage layer comprises silicon-rich silicon nitride.

### Claim 22 (depends on 16)

The storage transistor of claim 16, wherein the tunnel dielectric layer comprises silicon nitride, the barrier layer comprises cerium oxide, and the data storage layer comprises silicon-rich silicon nitride.

### Claim 23 (depends on 16)

The storage transistor of claim 16, wherein the tunnel dielectric layer comprises silicon oxide, the barrier layer comprises zirconium oxide, and the data storage layer comprises silicon-rich silicon nitride.

### Claim 24 (depends on 16)

The storage transistor of claim 16 wherein, when a voltage substantially less than the programming voltage is applied across the channel region and the gate electrode, electrons tunnel into the data storage layer by Fowler-Nordheim tunneling or a modified Fowler-Nordheim tunneling.

### Claim 25 (depends on 3)

The storage transistor of claim 3, further comprising a blocking dielectric layer between the data storage layer and the gate electrode.

### Claim 26 (depends on 25)

The storage transistor of claim 25, the blocking dielectric layer further comprises a layer of aluminum oxide.

### Claim 27 (depends on 26)

The storage transistor of claim 26, wherein the aluminum oxide layer in the blocking dielectric layer has a thickness between 2 nm and 5 nm.

### Claim 28 (depends on 1)

The storage transistor of claim 1, wherein the storage transistor is a quasi-volatile memory transistor.

### Claim 29 (depends on 28)

The storage transistor of claim 28, wherein storage transistor is one of a plurality of thin-film storage transistors formed in a NOR memory string.

### Claim 30 (depends on 29)

The storage transistor of claim 29, wherein the NOR memory string is one of a plurality of NOR memory strings in a 3-dimensional array.

### Claim 31 (depends on 1)

The storage transistor of claim 1, wherein the storage transistor is a quasi-volatile memory transistor.

### Claim 32 (depends on 31)

The storage transistor of claim 31, wherein storage transistor is one of a plurality of thin-film storage transistors formed in a NOR memory string.

### Claim 33 (depends on 32)

The storage transistor of claim 32, wherein the NOR memory string is one of a plurality of NOR memory strings in a 3-dimensional array.