# US 12,183,833 B2 · Flash memory device

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- Number: US 12,183,833 B2
- Document ID: US12183833B2
- Status: Granted
- Kind: B2
- Application number: 17/592,832
- Filed: 2022-02-04
- Published: 2022-05-19
- Granted: 2024-12-31
- Earliest claimed: 2019-03-19
- Assignees: Winbond Electronics Corp.
- Applicants: Winbond Electronics Corp.
- Inventors: Cheng-Ta Yang; Lu-Ping Chiang
- Web page: https://patentgrep.com/patent/US12183833B2

## CPC

- H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling}
- H10B 41/30: characterised by the memory core region
- H10B 41/40: characterised by the peripheral circuit region
- H10B 41/42: Simultaneous manufacture of periphery and memory cells
- H10B 41/49: comprising different types of peripheral transistor
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/514: {characterised by the insulating layers}
- H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A flash memory device is provided. The flash memory device includes a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, a first polycrystalline silicon layer and a second polycrystalline silicon layer. The first dielectric layer is formed on the substrate located in a first region of a peripheral region, the second dielectric layer is formed on the substrate located in a second region of the peripheral region, and the third dielectric layer is formed on the substrate located in an array region. A bottom surface of the third dielectric layer is lower than a bottom surface of the second dielectric layer. The first polycrystalline silicon layer is formed on the first and the second dielectric layers. The second polycrystalline silicon layer is formed on the third dielectric layer.

## Claims

### Claim 1

A flash memory device, comprising:
a substrate, wherein the substrate comprises an array region and a peripheral region, and the peripheral region comprises a first region, a second region, and a third region;
a first dielectric layer formed on the substrate in the first region of the peripheral region;
a surface nitrided second dielectric layer formed on the substrate in the second region of the peripheral region, wherein a thickness of the first dielectric layer is greater than a thickness of the surface nitrided second dielectric layer;
a third dielectric layer formed on the substrate in the array region and the third region of the peripheral region, wherein a bottom surface of the third dielectric layer is lower than a bottom surface of the surface nitrided second dielectric layer and a thickness of the third dielectric layer is greater than the thickness of the surface nitrided second dielectric layer;
a first polycrystalline silicon layer formed on the first dielectric layer and the surface nitrided second dielectric layer, wherein the first polycrystalline silicon layer comprises a first dopant; and
a second polycrystalline silicon layer formed on the third dielectric layer, wherein the second polycrystalline silicon layer comprises a second dopant,
wherein the second polycrystalline silicon layer in the array region is a floating gate, a first operating voltage corresponding to the first region is greater than a third operating voltage corresponding to the third region of the peripheral region and the array region, and the third operating voltage is greater than a second operating voltage corresponding to the second region.

### Claim 2 (depends on 1)

The flash memory device as claimed in claim 1, wherein the first dielectric layer and the third dielectric layer are surface nitrided oxide layers.

### Claim 3 (depends on 2)

The flash memory device as claimed in claim 2, wherein the first dielectric layer and the surface nitrided second dielectric layer are surface nitrided in the same process.

### Claim 4 (depends on 3)

The flash memory device as claimed in claim 3, wherein the third dielectric layer and the first dielectric layer are surface nitrided in different processes.

### Claim 5 (depends on 1)

The flash memory device as claimed in claim 1, wherein the thickness of the first dielectric layer is greater than the thickness of the third dielectric layer.

### Claim 6 (depends on 1)

The flash memory device as claimed in claim 1, wherein both the first dopant and the second dopant are boron.

### Claim 7 (depends on 1)

The flash memory device as claimed in claim 1, wherein the first polycrystalline silicon layer and the second polycrystalline silicon layer are formed in different processes.

### Claim 8 (depends on 1)

The flash memory device as claimed in claim 1, wherein the bottom surface of the third dielectric layer in the array region is coplanar with the bottom surface of the third dielectric layer in the third region.

### Claim 9 (depends on 8)

The flash memory device as claimed in claim 8, wherein the third region is located between the array region and the second region.

### Claim 10 (depends on 1)

The flash memory device as claimed in claim 1, wherein a top surface of the first polycrystalline silicon layer in the first region is higher than a top surface of the first polycrystalline silicon layer in the second region.

### Claim 11 (depends on 10)

The flash memory device as claimed in claim 10, wherein the top surface of the first polycrystalline silicon layer in the second region is higher than a top surface of the second polycrystalline silicon layer in the array region.

### Claim 12 (depends on 1)

The flash memory device as claimed in claim 1, wherein a top surface of the substrate in the array region is lower than a top surface of the substrate in the second region.

### Claim 13 (depends on 1)

The flash memory device as claimed in claim 1, wherein a bottom surface of the first dielectric layer is lower than the bottom surface of the surface nitrided second dielectric layer.

### Claim 14 (depends on 1)

The flash memory device as claimed in claim 1, wherein the bottom surface of the third dielectric layer is lower than a bottom surface of the first dielectric layer.

### Claim 15 (depends on 1)

The flash memory device as claimed in claim 1, wherein the first dielectric layer has a thickness in a range of 10-40 nm.

### Claim 16 (depends on 1)

The flash memory device as claimed in claim 1, wherein the surface nitrided second dielectric layer has a thickness in a range of 1-4 nm.

### Claim 17 (depends on 1)

The flash memory device as claimed in claim 1, wherein the third dielectric layer has a thickness in a range of 5-9 nm.