# US 12,183,831 B2 · Self-aligned contacts for thin film transistors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,831 B2 - Document ID: US12183831B2 - Status: Granted - Kind: B2 - Application number: 16/638,301 - Filed: 2017-09-29 - Published: 2020-07-16 - Granted: 2024-12-31 - Earliest claimed: 2017-09-29 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Van H. Le; Abhishek A. Sharma; Benjamin Chu-Kung; Gilbert Dewey; Ravi Pillarisetty; Miriam R. Reshotko; Shriram Shivaraman; Li Huey Tan; Tristan A. Tronic; Jack T. Kavalieros - Web page: https://patentgrep.com/patent/US12183831B2 ## CPC - H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 30/6704: {having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device} - H10D 30/6729: {characterised by the electrodes} - H10D 30/674: {characterised by the active materials} - H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)} - H10D 30/6745: {Polycrystalline or microcrystalline silicon} - H10D 30/6746: {Amorphous silicon} - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 64/01: Manufacture or treatment - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/60: wherein the TFTs are in active matrices - H10D 88/00: Three-dimensional [3D] integrated devices - H10D 88/01: {Manufacture or treatment} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Embodiments herein describe techniques for a semiconductor device, which may include a substrate, and a U-shaped channel above the substrate. The U-shaped channel may include a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area. A gate dielectric layer may be above the substrate and in contact with the channel bottom. A gate electrode may be above the substrate and in contact with the gate dielectric layer. A source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed. ## Claims ### Claim 1 A semiconductor device, comprising: a substrate; a U-shaped channel above the substrate, wherein the U-shaped channel includes a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area, the first channel wall intersects with the channel bottom at a first end and intersects with the source area at a second end, and the second channel wall intersects with the channel bottom at a first end and intersects with the drain area at a second end; a gate dielectric layer above the substrate and in contact with the channel bottom; a gate electrode above the substrate and in contact with the gate dielectric layer, wherein the gate electrode extends laterally beyond a lowermost portion of an outermost side of the first channel wall and laterally beyond a lowermost portion of an outermost side of the second channel wall of the U-shaped channel; and a source electrode in direct physical contact with a top surface of the source area but not in direct physical contact with a bottom surface of the source area, and a drain electrode in direct physical contact with a top surface of the drain area but not in direct physical contact with a bottom surface of the drain area, wherein a bottommost surface of the source electrode is above an uppermost surface of the source area, and a bottommost surface of the drain electrode is above an uppermost surface of the drain area, and wherein the source electrode is entirely within a width of the source area along a direction from the source area to the drain area and is vertically overlapping with the first channel wall of the U-shaped channel structure, and the drain electrode is entirely within a width of the drain area along the direction from the source area to the drain area and is vertically overlapping with the second channel wall of the U-shaped channel structure. ### Claim 2 (depends on 1) The semiconductor device of claim 1, further comprising: a first spacer next to the first channel wall, the source area, and the source electrode; and a second spacer next to the second channel wall, the drain area, and the drain electrode. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the gate electrode is a bottom gate electrode between the substrate and the channel bottom, the gate dielectric layer is between the gate electrode and the channel bottom, and the semiconductor device further includes a passivation layer between the first channel wall and the second channel wall. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the gate electrode is a top gate electrode above the channel bottom, and between the first channel wall and the second channel wall, and the gate dielectric layer is above the channel bottom, separating the first channel wall and the second channel from the gate electrode. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the gate electrode is a first gate electrode, and the semiconductor device further includes a second gate electrode, the first gate electrode is between the substrate and the channel bottom, and the second gate electrode is above the channel bottom, between the first channel wall and the second channel wall. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the gate dielectric layer includes silicon and oxygen, silicon and nitrogen, yttrium and oxygen, silicon, oxygen, and nitrogen, aluminum and oxygen, hafnium and oxygen, tantalum and oxygen, or titanium and oxygen. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein the U-shaped channel includes amorphous silicon, zinc oxide, amorphous germanium, polysilicon, poly germanium doped with boron, poly germanium doped with aluminum, poly germanium doped with phosphorous, poly germanium doped with arsenic, indium oxide, tin oxide, gallium oxide, indium gallium zinc oxide (IGZO), copper oxide, nickel oxide, cobalt oxide, indium tin oxide, tungsten disulphide, molybdenum disulphide, molybdenum selenide, black phosphorus, indium antimonide, graphene, graphyne, borophene, germanene, silicene, Si2BN, stanene, phosphorene, molybdenite, poly-III-V like InAs, InGaAs, InP, amorphous InGaZnO (a-IGZO), crystal-like InGaZnO (c-IGZO), GaZnON, ZnON, or C-Axis Aligned Crystal (CAAC). ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the gate electrode includes titanium (Ti), molybdenum (Mo), gold (Au), platinum (Pt), aluminum (Al), nickel (Ni), copper (Cu), chromium (Cr), or an alloy of Ti, Mo, Au, Pt, Al Ni, Cu, Cr, TiAIN, HfAIN, or InAlO. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein the substrate includes a silicon substrate, a glass substrate, a metal substrate, or a plastic substrate. ### Claim 10 (depends on 1) The semiconductor device of claim 1, wherein the semiconductor device is above an interconnect, and the interconnect is above the substrate. ### Claim 11 A computing device comprising: a processor; a memory device coupled to the processor, wherein the processor or the memory device includes a transistor, and the transistor includes: a U-shaped channel above a substrate, wherein the U-shaped channel includes a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area, the first channel wall intersects with the channel bottom at a first end and intersects with the source area at a second end, and the second channel wall intersects with the channel bottom at a first end and intersects with the drain area at a second end; a gate dielectric layer in contact with the channel bottom; a gate electrode in contact with the gate dielectric layer, wherein the gate electrode extends laterally beyond a lowermost portion of an outermost side of the first channel wall and laterally beyond a lowermost portion of an outermost side of the second channel wall of the U-shaped channel; and a source electrode in direct physical contact with a top surface of the source area but not in direct physical contact with a bottom surface of the source area, and a drain electrode in direct physical contact with a top surface of the drain area but not in direct physical contact with a bottom surface of the drain area, wherein a bottommost surface of the source electrode is above an uppermost surface of the source area, and a bottommost surface of the drain electrode is above an uppermost surface of the drain area, and wherein the source electrode is entirely within a width of the source area along a direction from the source area to the drain area and is vertically overlapping with the first channel wall of the U-shaped channel structure, and the drain electrode is entirely within a width of the drain area along the direction from the source area to the drain area and is vertically overlapping with the second channel wall of the U-shaped channel structure. ### Claim 12 (depends on 11) The computing device of claim 11, further comprising: a first spacer next to the first channel wall, the source area, and the source electrode; and a second spacer next to the second channel wall, the drain area, and the drain electrode. ### Claim 13 (depends on 11) The computing device of claim 11, wherein the gate electrode is a bottom gate electrode between the substrate and the channel bottom, the gate dielectric layer is between the gate electrode and the channel bottom, and the semiconductor device further includes a passivation layer between the first channel wall and the second channel wall. ### Claim 14 (depends on 11) The computing device of claim 11, wherein the gate electrode is a top gate electrode above the channel bottom, and between the first channel wall and the second channel wall, and the gate dielectric layer is above the channel bottom, separating the first channel wall and the second channel from the gate electrode. ### Claim 15 (depends on 11) The computing device of claim 11, wherein the gate electrode is a first gate electrode, and the semiconductor device further includes a second gate electrode, the first gate electrode is between the substrate and the channel bottom, and the second gate electrode is above the channel bottom, between the first channel wall and the second channel wall. ### Claim 16 (depends on 11) The computing device of claim 11, wherein the computing device is a wearable device or a mobile computing device, the wearable device or the mobile computing device including one or more of an antenna, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera.