# US 12,183,826 B2 · Vertical field effect transistor with low-resistance bottom source-drain contact

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- Number: US 12,183,826 B2
- Document ID: US12183826B2
- Status: Granted
- Kind: B2
- Application number: 17/302,986
- Filed: 2021-05-18
- Published: 2021-09-02
- Granted: 2024-12-31
- Earliest claimed: 2018-11-30
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Choonghyun Lee; Soon-Cheon Seo; Injo Ok; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US12183826B2

## CPC

- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6728: {Vertical TFTs}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 64/01: Manufacture or treatment
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure, and a method of making the same includes a fin extending upward from a substrate, an epitaxially grown bottom source/drain region in direct contact with the substrate and a bottom portion of the fin. A bottom surface and sidewalls of a metal silicide layer are in direct contact with the epitaxially grown bottom source/drain region. A bottom spacer is located above and in direct contact with the metal silicide layer and a portion of the epitaxially grown bottom source/drain region not covered by the metal silicide layer, the bottom spacer surrounding the fin.

## Claims

### Claim 1

A semiconductor structure comprising:
a fin extending upward from a substrate;
a first portion of an epitaxially grown bottom source/drain region being parallel to and in direct contact with a portion of the substrate adjacent to the fin;
a second portion of the epitaxially grown bottom source/drain region being perpendicular to the substrate and in direct contact with a bottom portion of the fin;
a metal silicide layer extending horizontally above the first portion of the epitaxially grown source/drain region parallel to the substrate, the metal silicide layer being partially abutted by the second portion of the epitaxially grown bottom source/drain region, the metal silicide layer comprising a bottom surface and opposing sidewalls, the bottom surface of the metal silicide layer being above and in direct contact with the first portion of the epitaxially grown source/drain region, the opposing sidewalls of the metal silicide layer being in direct contact with the second portion of the epitaxially grown bottom source/drain region for preventing the metal silicide layer to contact the fin, a top surface of the metal silicide layer extending in a plane for an entire distance between the opposing sidewalls of the metal silicide layer and being coplanar with a top surface of the second portion of the epitaxially grown bottom source/drain region;
a bottom spacer above and in direct contact with the coplanar top surface of the metal silicide layer and the top surface of the second portion of the epitaxially grown bottom source/drain region;
a gate dielectric layer in direct contact with sidewalls of the fin;
a gate metal layer in direct contact with the gate dielectric layer; and
a top spacer above and in direct contact with the gate metal layer and the bottom spacer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the bottom spacer surrounds the fin.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, further comprising:
a first dielectric layer above the top spacer; and
an epitaxially grown top source/drain region on a top surface of the fin.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, further comprising:
a second dielectric layer above the first dielectric layer, the second dielectric layer comprising a top source/drain contact on the top source/drain region;
a bottom source/drain contact on the first portion of the epitaxially grown bottom source/drain region; and
a gate contact on the gate metal layer, wherein the bottom source/drain contact is in close proximity to the second portion of the epitaxially grown bottom source/drain region to reduce an on-resistance of the semiconductor structure.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the metal silicide layer comprises titanium silicide.

### Claim 6 (depends on 3)

The semiconductor structure of claim 3, wherein the epitaxially grown top source/drain region comprises a diamond shape.

### Claim 7

A semiconductor structure comprising:
a fin extending upward from a substrate;
a first portion of an epitaxially grown bottom source/drain region in direct contact with a portion of the substrate, the first portion of the epitaxially grown bottom source/drain region having a first thickness in a vertical direction;
a second portion of the epitaxially grown bottom source/drain region being in direct contact with the substrate and a bottom portion of the fin, the second portion of the epitaxially grown bottom source/drain region having a second thickness in the vertical direction greater than the first thickness;
a metal silicide layer comprising a bottom surface and opposing sidewalls, the bottom surface of the metal silicide layer being above and in direct contact with the first portion of the epitaxially grown source/drain region, the opposing sidewalls of the metal silicide layer being in direct contact with the second portion of the epitaxially grown bottom source/drain region, an entire top surface of the metal silicide layer in a horizontal direction being coplanar with a top surface of the second portion of the epitaxially grown bottom source/drain region;
a bottom spacer in direct contact with the top surface of the metal silicide layer and the top surface of the second portion of the epitaxially grown bottom source/drain region;
a gate dielectric layer in direct contact with sidewalls of the fin;
a gate metal layer in direct contact with the gate dielectric layer; and
a top spacer in direct contact with the gate metal layer and the bottom spacer.

### Claim 8 (depends on 7)

The semiconductor structure of claim 7, wherein the top surface of the metal silicide layer extends an entire distance between the opposing sidewalls of the metal silicide layer.

### Claim 9 (depends on 7)

The semiconductor structure of claim 7, wherein the top spacer is in direct contact with the gate dielectric layer.