# US 12,183,825 B2 · Thin film transistor including a hydrogen-blocking dielectric barrier and methods for forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,825 B2 - Document ID: US12183825B2 - Status: Granted - Kind: B2 - Application number: 18/432,574 - Filed: 2024-02-05 - Published: 2024-05-30 - Granted: 2024-12-31 - Earliest claimed: 2021-02-02 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company Limited - Inventors: Neil Quinn Murray; Mauricio Manfrini; Hung-Wei Li - Web page: https://patentgrep.com/patent/US12183825B2 ## CPC - H10D 30/6704: {having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device} - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 99/00: Subject matter not provided for in other groups of this subclass - H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)} - H10P 14/69391: {the material containing aluminium, e.g. Al2O3} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A thin film transistor includes an insulating matrix layer including an opening therein, a hydrogen-blocking dielectric barrier layer continuously extending over a bottom surface and sidewalls of the opening and over a top surface of the insulating matrix layer, a gate electrode located within the opening, a stack of a gate dielectric and a semiconducting metal oxide plate overlying the gate electrode and horizontally-extending portions of the hydrogen-blocking dielectric barrier layer that overlie the insulating matrix layer, and a source electrode and a drain electrode contacting a respective portion of a top surface of the semiconducting metal oxide plate. ## Claims ### Claim 1 A semiconductor device comprising: an insulating matrix layer including an opening therein and overlying a substrate; a hydrogen-blocking dielectric barrier layer extending over a horizontal plane including a bottom surface of the insulating matrix layer and contacting sidewalls of the opening; a gate electrode located within the opening on the hydrogen-blocking dielectric barrier layer; a stack of a gate dielectric and a semiconducting metal oxide plate overlying a top surface of the gate electrode and horizontally-extending portions of the hydrogen-blocking dielectric barrier layer that overlie the insulating matrix layer; and a source electrode and a drain electrode contacting respective portions of a top surface of the semiconducting metal oxide plate. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the gate electrode overlies a first horizontally-extending portion of the hydrogen-blocking dielectric layer. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the hydrogen-blocking dielectric barrier layer continuously extends over a top surface of the insulating matrix layer. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein: the source electrode overlies a second horizontally-extending portion of the hydrogen-blocking dielectric barrier layer; and the drain electrode overlies a third horizontally-extending portion of the hydrogen-blocking dielectric barrier layer that is laterally spaced from the second horizontally-extending portion of the hydrogen-blocking dielectric barrier layer by the first horizontally-extending portion of the hydrogen-blocking dielectric barrier layer. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the hydrogen-blocking dielectric barrier layer comprises a dielectric metal oxide liner including a dielectric metal oxide material, in contact with a first region of a bottom surface of the gate dielectric underlying the source electrode, and in contact with a second region of the bottom surface of the gate dielectric that underlies the drain electrode and is laterally spaced from the first region of the bottom surface of the gate dielectric by the gate electrode. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the hydrogen-blocking dielectric barrier layer comprises a dielectric metal oxide liner in direct contact with the insulating matrix layer at the sidewalls of the opening. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein the hydrogen-blocking dielectric barrier layer comprises a silicon nitride liner in direct contact with the insulating matrix layer at the sidewalls of the opening. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the hydrogen-blocking dielectric barrier layer comprises a silicon nitride liner in contact with the gate electrode and spaced from the insulating matrix layer by a dielectric metal oxide liner. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein: the hydrogen-blocking dielectric barrier layer has a same area as the gate electrode; and the gate electrode contacts sidewalls of the insulating matrix layer. ### Claim 10 (depends on 1) The semiconductor device of claim 1, further comprising a capping hydrogen-blocking dielectric barrier layer comprising a capping dielectric metal oxide material and contacting a portion of a top surface of the semiconducting metal oxide plate. ### Claim 11 (depends on 1) The semiconductor device of claim 1, wherein: the substrate comprises a single crystalline silicon substrate; lower-level dielectric material layers embedding lower-level metal interconnect structures and located between the single crystalline silicon substrate and the insulating matrix layer; and field effect transistors including a respective portion of the single crystalline silicon substrate as a channel are embedded within the lower-level dielectric material layers, and are electrically connected to at least one of the gate electrode, the source electrode, and the drain electrode. ### Claim 12 A semiconductor device comprising: a single crystalline silicon substrate; field effect transistors including a respective portion of the single crystalline silicon substrate as a respective channel; lower-level dielectric material layers overlying the field effect transistors and embedding lower-level metal interconnect structures therein; an insulating matrix layer overlying the lower-level dielectric material layers and including an opening therein; a hydrogen-blocking dielectric barrier layer overlying the insulating material layer; a gate electrode located within the opening on the hydrogen-blocking dielectric barrier layer; and a stack of a gate dielectric and a semiconducting metal oxide plate overlying a top surface of the gate electrode and horizontally-extending portions of the hydrogen-blocking dielectric barrier layer that overlie the insulating matrix layer. ### Claim 13 (depends on 12) The semiconductor structure of claim 12, wherein the hydrogen-blocking dielectric barrier layer extends over a horizontal plane including a bottom surface of the insulating matrix layer and has a bottommost surface within the horizontal plane. ### Claim 14 (depends on 12) The semiconductor structure of claim 12, further comprising a source electrode and a drain electrode contacting respective portions of a top surface of the semiconducting metal oxide plate, wherein the lower-level interconnect structures are electrically connected to at least one of the gate electrode, the source electrode, and the drain electrode. ### Claim 15 (depends on 14) The semiconductor device of claim 14, further comprising: a top gate dielectric contacting a top surface of the semiconducting metal oxide plate; a top gate electrode overlying the top gate dielectric; a backside electrode contact via structure contacting a top surface of the gate electrode, wherein top surfaces of the source electrode, the drain electrode, the top gate electrode, and the backside electrode contact via structure are located within a same horizontal plane. ### Claim 16 A method of forming a semiconductor device, comprising: forming a combination of an insulating matrix layer, a hydrogen-blocking dielectric barrier layer, and a gate electrode over a substrate, wherein the gate electrode is laterally surrounded by vertically-extending portions of the hydrogen-blocking dielectric barrier layer and by the insulating matrix layer; forming a stack of a gate dielectric and a semiconducting metal oxide plate over the gate electrode; and forming a source electrode and a drain electrode on end portions of the semiconducting metal oxide plate. ### Claim 17 (depends on 16) The method of claim 16, further comprising forming a dielectric material layer over the semiconducting metal oxide plate directly on a portion of a top surface of the hydrogen-blocking dielectric barrier layer, wherein the source electrode and the drain electrode are formed through the dielectric material layer. ### Claim 18 (depends on 16) The method of claim 16, further comprising forming an opening in an upper portion of the insulating matrix layer, wherein: the hydrogen-blocking dielectric barrier layer is formed on physically exposed surfaces of the insulating matrix layer in the opening and over a top surface of the insulating matrix layer; and the gate electrode is formed within the opening on the hydrogen-blocking dielectric barrier layer. ### Claim 19 (depends on 18) The method of claim 18, wherein: the hydrogen-blocking dielectric barrier layer comprises a dielectric metal oxide liner including a dielectric metal oxide material; the gate dielectric is formed directly on a top surface of the gate electrode and directly on horizontally-extending portions of the dielectric metal oxide liner; and the dielectric metal oxide liner comprises a material selected from aluminum oxide and a dielectric transition metal oxide. ### Claim 20 (depends on 18) The method of claim 18, further comprising forming a capping hydrogen-blocking dielectric barrier layer comprising an additional dielectric metal oxide material on a top surface of the semiconducting metal oxide plate.