# US 12,183,823 B2 · Fin field-effect transistor with a gate structure having a dielectric protection layer

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- Number: US 12,183,823 B2
- Document ID: US12183823B2
- Status: Granted
- Kind: B2
- Application number: 17/868,999
- Filed: 2022-07-20
- Published: 2022-11-10
- Granted: 2024-12-31
- Earliest claimed: 2020-06-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chun-Neng Lin; Jian-Jou Lian; Ming-Hsi Yeh
- Web page: https://patentgrep.com/patent/US12183823B2

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/01: Manufacture or treatment
- H10D 64/01354: {passivation or protection of the electrode, e.g. using re-oxidation}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10W 20/092: {by smoothing the dielectric parts}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor fin. The semiconductor device includes a gate spacer over the semiconductor fin. A lower portion of the gate spacer surrounds a first region and an upper portion of the gate spacer surrounds a second region. The semiconductor device includes a gate dielectric within the first region. The semiconductor device includes a metal gate within the first region. The semiconductor device includes a dielectric protection layer, in contact with the gate dielectric layer, that includes a first portion within the second region and a second portion lining a top surface of the metal gate.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor fin;
a gate spacer over the semiconductor fin, wherein a lower portion of the gate spacer surrounds a first region and an upper portion of the gate spacer surrounds a second region;
a gate dielectric within the first region;
a metal gate within the first region;
a source/drain feature in the semiconductor fin adjacent to the metal gate;
an etch-stop layer overlaying the source/drain feature, a portion of the etch-stop layer laterally extending between a sidewall of the source/drain feature and the gate spacer;
a dielectric protection layer in contact with the gate dielectric, the dielectric protection layer including a first portion within the second region and a second portion lining a top surface of the metal gate;
a first dielectric layer over the dielectric protection layer;
a second dielectric layer adjacent the gate spacer, wherein top surfaces of the first dielectric layer, the second dielectric layer, and the dielectric protection layer are coplanar; and
a source/drain contact embedded in the second dielectric layer, wherein a portion of the second dielectric layer laterally separates the source/drain contact from the gate spacer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the gate dielectric includes at least one high-k dielectric material and the dielectric protection layer includes the same high-k dielectric material as the gate dielectric.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the dielectric protection layer includes a material selected from the group consisting of a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or combinations thereof.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the dielectric protection layer includes a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and combinations thereof.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising a gate contact extending through the second portion of the dielectric protection layer to electrically connect to the metal gate.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the gate contact is electrically isolated from the source/drain contact by at least the first portion of the dielectric protection layer.

### Claim 7

A semiconductor device, comprising:
a semiconductor fin;
a lightly doped drain region in the semiconductor fin;
a metal gate over the semiconductor fin;
a gate spacer over the semiconductor fin and extending along a sidewall of the metal gate, wherein the gate spacer includes a lower portion and an upper portion over the lower portion, and wherein the sidewall of the metal gate is adjacent the lower portion;
a source/drain feature in the lightly doped drain region, wherein the gate spacer is vertically aligned with a sidewall of the lightly doped drain region;
a dielectric protection layer having a sidewall adjacent to the upper portion of the gate spacer and a bottom surface contacting a top surface of the metal gate, the dielectric protection layer including a metal silicate material; and
a dielectric layer fully embedded in the dielectric protection layer, such that top surfaces of the dielectric protection layer and the dielectric layer are coplanar, the dielectric layer including a low-k dielectric material.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, further comprising a gate dielectric layer between the metal gate and the gate spacer, wherein the bottom surface of the dielectric protection layer contacts a top surface of the gate dielectric layer.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the dielectric protection layer and the gate dielectric layer include the same dielectric material.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the sidewall of the dielectric protection layer and a sidewall of the gate dielectric layer both directly contact the gate spacer.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein the gate dielectric layer includes a high-k metal oxide material.

### Claim 12 (depends on 7)

The semiconductor device of claim 7, wherein the dielectric layer includes silicon oxide.

### Claim 13 (depends on 7)

The semiconductor device of claim 7, further comprising a gate contact over the metal gate, wherein the gate contact extends through the bottom surface of the dielectric protection layer to directly contact the metal gate.

### Claim 14 (depends on 7)

The semiconductor device of claim 7, further comprising:
an interlayer dielectric layer adjacent the dielectric protection layer; and
a source/drain contact embedded in the interlayer dielectric layer, wherein the source/drain contact is separated from the dielectric protection layer by a portion of the interlayer dielectric layer.

### Claim 15

A semiconductor device, comprising:
a semiconductor fin;
a gate spacer over the semiconductor fin, wherein the gate spacer includes an upper portion over a lower portion;
a gate dielectric over the semiconductor fin;
a metal gate over the gate dielectric and adjacent the lower portion of the gate spacer, wherein a top surface of the gate spacer is above a top surface of each of the metal gate and the gate dielectric;
a source/drain feature in the semiconductor fin adjacent to the metal gate;
an etch-stop layer over the source/drain feature, a portion of the etch-stop layer directly contacting both a sidewall of the gate spacer and a sidewall of the source/drain feature;
a dielectric protection layer over the metal gate, wherein the dielectric protection layer includes a sidewall portion extending along the upper portion of the gate spacer and a bottom portion extending across the top surface of each of the metal gate and the gate dielectric, and wherein the dielectric protection layer includes a metal silicate;
an interlayer dielectric (ILD) layer adjacent the gate spacer, wherein top surfaces of the ILD layer and the dielectric protection layer are leveled; and
a source/drain contact embedded in the ILD layer, a portion of the ILD layer laterally separating the source/drain contact from the gate spacer.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the gate dielectric and the dielectric protection layer both directly contact the gate spacer.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the gate dielectric and the dielectric protection layer have the same composition, and wherein the gate spacer and the dielectric protection layer have different compositions.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein the top surface of the dielectric protection layer is leveled with a top surface of the gate spacer.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, further comprising a gate contact electrically connected to the metal gate, wherein the gate contact extends through the bottom portion of the dielectric protection layer to directly contact the metal gate.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein the gate contact is electrically isolated from the source/drain contact by at least the sidewall portion of the dielectric protection layer.