# US 12,183,822 B2 · MOSFET structure with controllable channel length by forming lightly doped drains without using ion implantation

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- Number: US 12,183,822 B2
- Document ID: US12183822B2
- Status: Granted
- Kind: B2
- Application number: 17/314,233
- Filed: 2021-05-07
- Published: 2022-10-06
- Granted: 2024-12-31
- Earliest claimed: 2021-04-06
- Assignees: Invention And Collaboration Laboratory Pte. Ltd.; Etron Technology, Inc.
- Applicants: Invention And Collaboration Laboratory Pte. Ltd.; Etron Technology, Inc.
- Inventors: Chao-Chun Lu
- Web page: https://patentgrep.com/patent/US12183822B2

## CPC

- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 30/022: {having lightly-doped source or drain extensions selectively formed at the sides of the gates}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10P 14/276: {Lateral overgrowth}
- H10P 14/3438: {Doping during depositing}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention provides a new MOSFET structure with controllable channel length by forming lightly doped drains without using ion implantation. The MOSFET structure comprises a semiconductor wafer substrate with a semiconductor surface, a gate structure over the semiconductor surface, a channel region under the semiconductor surface, and a first conductive region electrically coupled to the channel region. The first conductive region comprises a lightly doped drain region independent from the semiconductor wafer substrate.

## Claims

### Claim 1

A MOSFET structure comprising:
a semiconductor wafer substrate with a semiconductor surface;
a gate structure over the semiconductor surface;
a channel region under the semiconductor surface;
a first conductive region surrounded by a shallow trench isolation (STI) region and electrically coupled to the channel region; and
a first trench formed below the semiconductor surface and defined by an edge of the channel region and an edge of the STI region which face with each other, wherein the first trench includes a first edge facing the edge of the channel region and a second edge opposing to the first edge, the second edge is aligned with the edge of the STI region;
wherein the first conductive region comprises a lightly doped drain region independent from the semiconductor wafer substrate and a heavily doped drain region; the lightly doped drain region at least laterally extends from the first edge of the first trench and the heavily doped drain region at least laterally extends from the lightly doped drain region, and the first trench accommodates the lightly doped drain region;
wherein the first conductive region comprises a first most external edge facing to the edge of the channel region and a second most external edge opposite to the first most external edge, wherein the second most external edge is faced to and limited by the edge of the STI region, wherein the first edge of the first trench is controllable to align or substantially align with an edge of the gate structure.

### Claim 2 (depends on 1)

The MOSFET structure in claim 1, wherein the lightly doped drain region abuts against the channel region.

### Claim 3 (depends on 1)

The MOSFET structure in claim 1, wherein the lightly doped drain region is a L-shape LDD comprising a side LDD region covering a sidewall of the first trench and a bottom LDD covering a bottom wall of the first trench.

### Claim 4 (depends on 3)

The MOSFET structure in claim 3, wherein the side LDD region abuts against the channel region, and the first conductive region further comprises a highly doped semiconductor region abutting against the side LDD region and the bottom LDD region.

### Claim 5 (depends on 4)

The MOSFET structure in claim 4, wherein the heavily doped semiconductor region is shielded from the semiconductor wafer substrate.

### Claim 6 (depends on 3)

The MOSFET structure in claim 3, wherein the sidewall of the first trench is aligned or substantially aligned with an edge of the gate structure.

### Claim 7 (depends on 3)

The MOSFET structure in claim 3, wherein the channel region is a fin structure, and a vertical depth of the channel region is substantially the same as that of side LDD region.

### Claim 8 (depends on 3)

The MOSFET structure in claim 3, wherein the L-shape LDD is formed by selective epitaxy growth or atomic layer deposition, the channel region is a fin structure, and the side LDD region is contacted to a first facet of the fin structure.

### Claim 9 (depends on 3)

The MOSFET structure in claim 3, wherein the L-shape LDD is formed without ion implementation, the channel region is a fin structure, and the side LDD region is contacted to a first facet of the fin structure.

### Claim 10

A MOSFET structure comprising:
a semiconductor wafer substrate with a semiconductor surface;
a gate structure over the semiconductor surface;
a channel region under the semiconductor surface;
a first conductive region surrounded by a STI region, comprising a lightly doped drain region independent from the semiconductor wafer substrate and a heavily doped drain region, and electrically coupled to the channel region;
a first trench formed below the semiconductor surface and defined by an edge of the channel region and an edge of the STI region which face with each other, wherein the first trench includes a first edge facing the edge of the channel region and a second edge opposing to the first edge, the second edge is aligned with the edge of the STI region, wherein the lightly doped drain region at least laterally extends from the first edge of the first trench; and the heavily doped drain region at least laterally extends from the lightly doped drain region; and
wherein the first edge of the first trench is controlled by a thickness of a thermal oxidation layer;
wherein the first conductive region comprises a first most external edge facing to the edge of the channel region and a second most external edge opposite to the first most external edge, wherein the second most external edge is faced to and limited by the edge of the STI region.

### Claim 11 (depends on 10)

The MOSFET structure in claim 10, wherein the first edge of the first trench is revealed after the thermal oxidation layer is removed.

### Claim 12

A MOSFET structure comprising:
a semiconductor wafer substrate with a semiconductor surface;
a gate structure over the semiconductor surface;
a channel region under the semiconductor surface;
a first conductive region surrounded by a STI region and electrically coupled to the channel region; and
a first trench formed below the semiconductor surface and defined by an edge of the channel region and an edge of the STI region which face with each other, wherein the first trench includes a first edge facing the edge of the channel region and a second edge opposing to the first edge, the second edge is aligned with the edge of the STI region;
wherein the first conductive region comprises a lightly doped drain region independent from the semiconductor wafer substrate and a heavily doped drain region; and the first trench accommodates the lightly doped drain region; wherein a vertical edge of the lightly doped drain region is parallel to a vertical edge of the gate structure;
wherein the first conductive region comprises a first most external edge facing to the edge of the channel region and a second most external edge opposite to the first most external edge, wherein the second most external edge is faced to and limited by the edge of the STI region; the first most external edge is controllable to align or substantially align with an edge of the gate structure.

### Claim 13 (depends on 12)

The MOSFET structure in claim 12, wherein the vertical edge of the lightly doped drain region is substantially aligned with the vertical edge of the gate structure.