# US 12,183,821 B2 · Single transistor with double gate structure for adjustable firing threshold voltage, and neuromorphic system using the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,821 B2 - Document ID: US12183821B2 - Status: Granted - Kind: B2 - Application number: 17/346,372 - Filed: 2021-06-14 - Published: 2021-12-16 - Granted: 2024-12-31 - Earliest claimed: 2020-06-15 - Assignees: Korea Advanced Institute of Science and Technology - Applicants: Korea Advanced Institute of Science and Technology - Inventors: Yang-Kyu Choi; Joon-Kyu Han - Web page: https://patentgrep.com/patent/US12183821B2 ## CPC - G06N 3/049: Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs - H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)} - G06N 3/063: using electronic means - G06N 3/065: Analogue means - H10D 30/6737: {characterised by the electrode materials} - H10D 30/6743: {Silicon} - H10D 30/711: {having floating bodies} - G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Disclosed is a single transistor with a double gate structure for an adjustable firing threshold voltage and a neuromorphic system using the same. A single transistor neuron with a double gate structure according to an example embodiment includes a barrier material layer formed on a semiconductor substrate and comprising a hole barrier material or an electron barrier material; a floating body layer formed on the barrier material layer; a source and a drain formed at both sides of the floating body layer, respectively; a driving gate formed at a first side of the floating body layer without contacting the source and the drain; a control gate formed at a second side of the floating body layer without contacting the source and the drain; and a gate insulating film formed between the floating body layer and the driving gate and between the floating body layer and the control gate. ## Claims ### Claim 1 A single transistor neuron with a double gate structure, the single transistor neuron comprising: a barrier material layer formed on a semiconductor substrate and comprising a hole barrier material or an electron barrier material; a floating body layer formed on the barrier material layer, the floating body layer having first, second, third, and fourth sides; a source and a drain formed at the third and fourth sides of the floating body layer, respectively; a driving gate formed at the first side of the floating body layer without contacting the source and the drain; a control gate formed at the second side of the floating body layer without contacting the source and the drain; and a gate insulating film formed between the floating body layer and the driving gate and between the floating body layer and the control gate, wherein the single transistor neuron with the double gate structure integrates a signal when a current signal is applied to the source or the drain and outputs a voltage signal in a form of a spike from the source or the drain if the integrated signal reaches a predetermined level or more. ### Claim 2 (depends on 1) The single transistor neuron of claim 1, wherein the barrier material layer is formed using one of buried oxide, a buried n-well in the case of a p-type body, a buried p-well in the case of an n-type body, buried SiC, and buried SiGe. ### Claim 3 (depends on 1) The single transistor neuron of claim 1, wherein the floating body layer accumulates holes or electrons and is formed using one of silicon, germanium, silicon germanium, and a group III-V compound semiconductor. ### Claim 4 (depends on 1) The single transistor neuron of claim 1, wherein the semiconductor substrate is configured to act as a back gate. ### Claim 5 (depends on 1) The single transistor neuron of claim 1, wherein the source and the drain are formed using one of n-type silicon, p-type silicon, and metal silicide. ### Claim 6 (depends on 5) The single transistor neuron of claim 5, wherein the source and the drain formed using the n-type silicon or the p-type silicon are formed using at least one of diffusion, solid-phase diffusion, epitaxial growth, selective epitaxial growth, ion implantation, and subsequent annealing treatment. ### Claim 7 (depends on 5) The single transistor neuron of claim 5, wherein the source and the drain formed using the metal silicide comprises the metal silicide formed using one of tungsten (W), titanium (Ti), cobalt (Co), nickel (Ni), erbium (Er), ytterbium (Yb), samarium (Sm), yttrium (Y), gadolinium (Gd), terbium (Tb), cerium (Ce), platinum (Pt), lead (Pb), and iridium (Ir), and enhances a junction using dopant segregation. ### Claim 8 (depends on 1) The single transistor neuron of claim 1, wherein the driving gate and the control gate are formed using one of n-type polysilicon, p-type polysilicon, aluminum (Al), molybdenum (Mo), chromium (Cr), palladium (Pd), platinum (Pt), nickel (Ni), titanium (Ti), tantalum (Ta), tungsten (W), silver (Ag), titanium nitride (TiN), tantalum nitride (TaN), and any combination thereof. ### Claim 9 (depends on 1) The single transistor neuron of claim 1, wherein the gate insulating film is formed using one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, hafnium oxynitride, zinc oxide, zirconium oxide, hafnium zirconium oxide (HZO), and any combination thereof. ### Claim 10 (depends on 1) The single transistor neuron of claim 1, wherein the driving gate and the control gate are independently separate from each other and formable into different types, and the gate insulating film in contact with the driving gate and the gate insulating film in contact with the control gate are formable using different types, electric constants, and thicknesses. ### Claim 11 (depends on 1) The single transistor neuron of claim 1, wherein the single transistor neuron with the double gate structure implements an inhibitory function of inhibiting a spike action of a neuron by inputting an inhibitory signal to the driving gate. ### Claim 12 (depends on 1) The single transistor neuron of claim 1, wherein the single transistor neuron with the double gate structure maintains homeostasis of a neuron by changing a voltage that is applied to the control gate and thereby adjusting a firing threshold voltage of the neuron. ### Claim 13 An operation method of a single transistor neuron with a double gate structure comprising a driving gate and a control gate independently separate from each other, the method comprising: inputting a current signal from a previous synaptic device to a source or a drain; storing charge by the current signal in a transistor; outputting a voltage signal in a form of a spike when a source voltage or a drain voltage increasing according to the stored charge reaches a firing threshold voltage or more; and adjusting the firing threshold voltage through the control gate if a frequency of the output voltage signal deviates from a preset normal range, wherein the single transistor neuron with the double gate structure integrates a signal when a current signal is applied to the source or the drain and outputs a voltage signal in a form of a spike from the source or the drain if the integrated signal reaches a predetermined level or more. ### Claim 14 A neuromorphic system comprising a single transistor neuron with a double gate structure comprising a driving gate and a control gate independently separate from each other, wherein the single transistor neuron is capable of adjusting a firing threshold voltage through the control gate and wherein the single transistor neuron with the double gate structure integrates a signal when a current signal is applied to the source or the drain and outputs a voltage signal in a form of a spike from the source or the drain if the integrated signal reaches a predetermined level or more. ### Claim 15 (depends on 14) The neuromorphic system of claim 14, wherein the neuromorphic system comprises at least one additional component among a resistance, a capacitor, another transistor, and an inverter in addition to the single transistor neuron. ### Claim 16 (depends on 14) The neuromorphic system of claim 14, wherein the neuromorphic system comprises any one synaptic device among a resistive random-access memory (RRAM), a memristor, a charge trap flash memory, a phase change material (PCM), and a ferroelectric RAM (FeRAM) in addition to the single transistor neuron. ### Claim 17 A single transistor neuron with a double gate structure, the single transistor neuron comprising: a barrier material layer formed on a semiconductor substrate and comprising a hole barrier material or an electron barrier material; a floating body layer formed on the barrier material layer, the floating body layer having first, second, third, and fourth sides; a source and a drain formed at the third and fourth sides of the floating body layer, respectively; a driving gate formed at the first side of the floating body layer without contacting the source and the drain; a control gate formed at the second side of the floating body layer without contacting the source and the drain; and a gate insulating film formed between the floating body layer and the driving gate and between the floating body layer and the control gate, wherein the single transistor neuron with the double gate structure implements an inhibitory function of inhibiting a spike action of a neuron by inputting an inhibitory signal to the driving gate, integrates the signal when a current signal is applied to the source or drain, and outputs a voltage signal in the form of a spike from the source or drain when the integrated signal reaches a predetermined level or higher.