# US 12,183,819 B2 · Silicon carbide semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,183,819 B2 - Document ID: US12183819B2 - Status: Granted - Kind: B2 - Application number: 18/170,938 - Filed: 2023-02-17 - Published: 2023-06-29 - Granted: 2024-12-31 - Earliest claimed: 2020-03-17 - Assignees: Fuji Electric Co., Ltd. - Applicants: Fuji Electric Co., Ltd. - Inventors: Hiroyuki Fujisawa; Akimasa Kinoshita - Web page: https://patentgrep.com/patent/US12183819B2 ## CPC - H10D 84/148: {the built-in components being breakdown diodes, e.g. Zener diodes} - H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes} - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)} - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10D 62/307: {the doping variations being parallel to the channel lengths} - H10D 84/144: {in antiparallel diode configurations} - H10D 62/157: {Impurity concentrations or distributions} - H10D 62/8325: {Silicon carbide} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, gate insulating films, gate electrodes, an insulating film, first electrodes, a second electrode, and trenches. The first semiconductor regions and the second semiconductor regions are periodically disposed apart from one another in a first direction in which the trenches extend in a stripe pattern. ## Claims ### Claim 1 A semiconductor device, comprising: a plurality of trenches provided at a first main surface of a semiconductor base that includes a semiconductor substrate of a first conductivity type, the plurality of trenches including a plurality of longitudinal portions that each extend in a first direction; a plurality of first semiconductor regions of the first conductivity type, each first semiconductor region being selectively provided at the first main surface of the semiconductor base and being in contact with a sidewall of one of the plurality of longitudinal portions; a plurality of bottom regions of a second conductivity type, respectively in contact with bottoms of respective ones of the plurality of longitudinal portions; and a second semiconductor region of the second conductivity type, provided along a sidewall of a corresponding one of the plurality of longitudinal portions and extending from the first main surface of the semiconductor base to a corresponding one of the plurality of bottom regions that is in contact with the corresponding one of the plurality of longitudinal portions, wherein the second semiconductor region includes a plurality of upper portions thereof that are periodically exposed from the first main surface of the semiconductor base in the first direction, and on the first main surface, in the first direction, an interval of, among the plurality of upper portions of the second semiconductor region, an adjacent two upper portions that are adjacent in the first direction is greater than a length of each of the plurality of upper portions of the second semiconductor region. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the second semiconductor region includes a plurality of portions of the second semiconductor region that are periodically provided in the first direction. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the second semiconductor region includes a plurality of upper portions of the second semiconductor region that are periodically exposed from the first main surface of the semiconductor base in the first direction, and on the first main surface, in the first direction, an interval of, among the plurality of upper portions of the second semiconductor region, an adjacent two upper portions that are adjacent in the first direction is at least 2.514 μm. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the second semiconductor region includes: a semiconductor layer of the second conductivity type; a plurality of high-concentration semiconductor regions of the second conductivity type, selectively provided at the first main surface of the semiconductor base, each high-concentration semiconductor region having an impurity concentration higher than an impurity concentration of the semiconductor layer; a connecting region of the second conductivity type that connects the semiconductor layer to the corresponding one of the plurality of bottom regions. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein each high-concentration semiconductor region is provided across a mesa region between, among the plurality of longitudinal portions, an adjacent two longitudinal portions that are adjacent in a second direction orthogonal to the first direction. ### Claim 6 (depends on 4) The semiconductor device according to claim 4, wherein each high-concentration semiconductor region is in contact with only one of an adjacent two longitudinal portions among the plurality of longitudinal portions that are adjacent in a second direction orthogonal to the first direction. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein at least one of the plurality of first semiconductor regions is provided across a mesa region between an adjacent two longitudinal portions among the plurality of longitudinal portions that are adjacent in a second direction orthogonal to the first direction. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, further comprising: an interlayer insulating film provided on the first main surface of the semiconductor base; a plurality of contact holes that penetrate through the interlayer insulating film in a depth direction; a source electrode that is in contact with the plurality of first semiconductor regions and the second semiconductor region, via the plurality of contact holes. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor device is a trench-type SiC-MOSFET. ### Claim 10 A semiconductor device, comprising: a plurality of trenches provided at a first main surface of a semiconductor base that includes a semiconductor substrate of a first conductivity type, the plurality of trenches including a plurality of longitudinal portions that each extend in a first direction; a plurality of mesa regions, each being provided between an adjacent two longitudinal portions among the plurality of longitudinal portions that are adjacent in a second direction orthogonal to the first direction; and a plurality of bottom regions of a second conductivity type, respectively in contact with bottoms of respective ones of the plurality of longitudinal portions, wherein each mesa region includes: a semiconductor layer of the second conductivity type; a plurality of first semiconductor regions of the first conductivity type, each first semiconductor region being selectively provided at the first main surface of the semiconductor base and in contact with a sidewall of one of the adjacent two longitudinal portions; and a plurality of connecting regions of the second conductivity type that are periodically provided in the first direction, the plurality of connecting regions connecting the semiconductor layer to bottom regions that are respectively in contact with the adjacent two longitudinal portions forming said each mesa region, the semiconductor layer includes a plurality of upper portions thereof that are periodically exposed from the first main surface of the semiconductor base in the first direction, and on the first main surface, in the first direction, an interval of, among the plurality of upper portions of the semiconductor layer, an adjacent two upper portions that are adjacent in the first direction is greater than a length of each of the plurality of upper portions of the semiconductor layer. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, wherein each connecting region extends from one to the other of the adjacent two longitudinal portions. ### Claim 12 (depends on 10) The semiconductor device according to claim 10, wherein an impurity concentration of each of the plurality of bottom regions is higher than an impurity concentration of the semiconductor layer. ### Claim 13 (depends on 10) The semiconductor device according to claim 10, wherein an impurity concentration of each of the plurality of connecting regions is higher than an impurity concentration of the semiconductor layer. ### Claim 14 (depends on 10) The semiconductor device according to claim 10, further comprising a gate electrode embedded in each of the plurality of longitudinal portions via a gate insulating film. ### Claim 15 (depends on 14) The semiconductor device according to claim 14, wherein the plurality of mesa regions include: a plurality of first mesa regions, each first mesa region including the semiconductor layer and the plurality of first semiconductor regions, both of which are in contact with the gate insulating film; and a plurality of second mesa regions, each second mesa region including the plurality of connecting regions that respectively extend between the adjacent two longitudinal portions that form said each second mesa region. ### Claim 16 A semiconductor device, comprising: a plurality of trenches provided at a first main surface of a semiconductor base that includes a semiconductor substrate of a first conductivity type, the plurality of trenches including a plurality of longitudinal portions that respectively extend in a first direction; a plurality of first mesa regions respectively provided between a first adjacent two longitudinal portions among the plurality of longitudinal portions that are adjacent in a second direction orthogonal to the first direction; a plurality of second mesa regions respectively provided between a second adjacent two longitudinal portions among the plurality of longitudinal portions that are adjacent in the second direction; and a gate electrode embedded in each of the plurality of longitudinal portions via a gate insulating film, wherein each of the plurality of first mesa regions includes: a plurality of first semiconductor regions of the first conductivity type, each first semiconductor region being selectively provided at the first main surface of the semiconductor base and being in contact with the gate insulating film; and a semiconductor layer of a second conductivity type that is in contact with the gate insulating film under the plurality of first semiconductor regions, and each of the plurality of second mesa regions includes: a second semiconductor region of the second conductivity type, extending from a bottom of one of the second adjacent two longitudinal portions to a bottom of another of the second adjacent two longitudinal portions, the semiconductor layer includes a plurality of upper portions thereof that are periodically exposed from the first main surface of the semiconductor base in the first direction, and on the first main surface, in the first direction, an interval of, among the plurality of upper portions of the semiconductor layer, an adjacent two upper portions that are adjacent in the first direction is greater than a length of each of the plurality of upper portions of the semiconductor layer. ### Claim 17 (depends on 16) The semiconductor device according to claim 16, wherein the plurality of first mesa regions are provided between an adjacent two second mesa regions among the plurality of second mesa regions that are adjacent in the second direction. ### Claim 18 (depends on 16) The semiconductor device according to claim 16, further comprising a plurality of bottom regions of the second conductivity type, respectively in contact with bottoms of respective ones of the plurality of longitudinal portions, wherein the second semiconductor region of each of the plurality of second mesa regions includes a plurality of connecting regions of the second conductivity type that respectively connect the semiconductor layer to the plurality of bottom regions. ### Claim 19 (depends on 16) The semiconductor device according to claim 16, wherein the plurality of first mesa regions respectively function as a part of a MOS cell region, and the plurality of second mesa regions respectively function as a part of a diode cell region.