# US 12,183,811 B2 · Dual-gated memtransistor crossbar array, fabricating methods and applications of same

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- Number: US 12,183,811 B2
- Document ID: US12183811B2
- Status: Granted
- Kind: B2
- Application number: 17/036,428
- Filed: 2020-09-29
- Published: 2021-04-01
- Granted: 2024-12-31
- Earliest claimed: 2019-10-01
- Assignees: Northwestern University
- Applicants: Northwestern University
- Inventors: Mark C. Hersam; Vinod K. Sangwan; Hong-Sub Lee
- Web page: https://patentgrep.com/patent/US12183811B2

## CPC

- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 48/366: {Multistable devices; Devices having two or more distinct operating states}
- G06N 3/04: Architecture, e.g. interconnection topology
- G06N 3/0499: Feedforward networks
- G06N 3/065: Analogue means
- G06N 3/08: Learning methods
- G06N 3/09: Supervised learning
- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/003: {Cell access}
- G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- H10B 99/22: {including field-effect components}
- H10D 12/421: {on insulating layers or insulating substrates, e.g. thin-film IGBTs}
- H10D 30/481: {FETs having two-dimensional material channels, e.g. transition metal dichalcogenide [TMD] FETs}
- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10D 62/80: characterised by the materials
- H10D 62/883: {Transition metal dichalcogenides, e.g. MoSe2}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- G06N 3/049: Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 2213/53: Structure wherein the resistive material being in a transistor, e.g. gate
- G11C 2213/82: Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
- H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 62/40: Crystalline structures
- H10D 64/647: {Schottky drain or source electrodes for IGFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A memtransistor includes a top gate electrode and a bottom gate electrode; a polycrystalline monolayer film formed of an atomically thin material disposed between the top gate electrode and the bottom gate electrode; and source and drain electrodes spatial-apart formed on the polycrystalline monolayer film to define a channel in the polycrystalline monolayer film between the source and drain electrodes. The top gate electrode and the bottom gate electrode are capacitively coupled with the channel.

## Claims

### Claim 1

A memtransistor, comprising:
a bottom gate electrode;
a bottom dielectric layer formed on the bottom gate electrode layer;
a polycrystalline monolayer film formed of an atomically thin material disposed on the bottom dielectric layer, wherein the atomically thin material comprises two-dimensional (2D) semiconductor material, wherein the 2D semiconductor material comprises monochalcogenides comprising InSe or GaTe, or black phosphorus (BP), wherein the polycrystalline monolayer film contains grains having an average grain size of about 1 μm2;
a source electrode and a drain electrode spatial-apart formed on the bottom dielectric layer such that the polycrystalline monolayer film is disposed between the source electrode and the drain electrode to define a channel in the polycrystalline monolayer film therebetween;
a top dielectric layer formed on the polycrystalline monolayer film and extended over the source electrode and the drain electrode, such that each of the source electrode and the drain electrode is disposed between the bottom dielectric layer and the top dielectric layer; and
a top gate electrode formed on the top dielectric layer,
wherein the top gate electrode and the bottom gate electrode are capacitively coupled with the channel; and
wherein the memtransistor is a dual gated memtransistor characterized with a switching ratio between a low resistance state (LRS) and a high resistance state (HRS), wherein the switching ratio is a ratio of current (ILRS) of the dual gated memtransistor at the LRS to that (IHRS) of the dual gated memtransistor at the HRS, and wherein the dual gated memtransistor is configured such that the switching ratio increases with increasing a voltage of the bottom gate electrode.

### Claim 2 (depends on 1)

The memtransistor of claim 1, wherein the top gate electrode and the bottom gate electrode and the source and drain electrodes comprise a same conductive material or different conductive materials.

### Claim 3 (depends on 2)

The memtransistor of claim 2, wherein each of the top gate electrode and the bottom gate electrode and the source and drain electrodes is formed of gold (Au), titanium (Ti), aluminum (Al), nickel (Ni), chromium (Cr), and other conductive materials.

### Claim 4 (depends on 2)

The memtransistor of claim 2, wherein the bottom gate electrode is formed of doped silicon (Si).

### Claim 5 (depends on 1)

The memtransistor of claim 1, wherein the top dielectric layer and the bottom dielectric layer comprise a same dielectric material or different dielectric materials.

### Claim 6 (depends on 5)

The memtransistor of claim 5, wherein the top dielectric layer is formed of Al2O3, HfO2, ZrO2, or ZnO.

### Claim 7 (depends on 5)

The memtransistor of claim 5, wherein the bottom dielectric layer is formed of SiO2, or dielectrics including alumina, hafnia, or zirconia.

### Claim 8 (depends on 1)

The memtransistor of claim 1, wherein the memtransistor is configured to have bipolar resistive switching characteristics at different biases applied to the bottom gate electrode with the top gate electrode left floating.

### Claim 9 (depends on 1)

The memtransistor of claim 1, wherein the memtransistor is configured to have a memristive loop with minimal bottom gate bias hysteresis.

### Claim 10 (depends on 1)

The memtransistor of claim 1, wherein the memtransistor is configured such that both long-term potentiation (LTP) and long-term depression (LTD) are operably modulated as a function of a gate bias during writing, while an output current during reading is operably controlled as a function of the gate bias during reading without affecting an intrinsic state of the memtransistor.

### Claim 11 (depends on 1)

A circuitry, comprising one or more memtransistors according to claim 1.

### Claim 12 (depends on 1)

An electronic device, comprising one or more memtransistors according to claim 1.

### Claim 13

A crossbar array comprised of M columns and N rows of memtransistors, each of M and N being an integer greater than zero, comprising:
a bottom gate electrode layer;
a bottom dielectric layer formed on the bottom gate electrode layer;
a polycrystalline monolayer film formed of an atomically thin material formed on the bottom dielectric layer, wherein the atomically thin material comprises two-dimensional (2D) semiconductor material, wherein the polycrystalline monolayer film contains grains having an average grain size of about 1 μm2;
M+1 source-drain electrodes spatial-apart formed on the polycrystalline monolayer film along a column direction, wherein the polycrystalline monolayer film is patterned according to the M+1 source-drain electrodes to define M columns and N rows of channels therein, such that each two neighboring source-drain electrodes are coupled with N channels of a respective channel column between said two neighboring source-drain electrodes;
a top dielectric layer formed on the polycrystalline monolayer film and extended over the M+1 source-drain electrodes, such that each of the M+1 source-drain electrodes is disposed between the bottom dielectric layer and the top dielectric layer; and
N top gate electrodes formed on the top dielectric layer, crossing over the M+1 source-drain electrodes along a row direction, such that each top gate electrode is capacitively coupled with M channels of a respective channel row,
wherein each memtransistor is a dual gated memtransistor characterized with a switching ratio between a low resistance state (LRS) and a high resistance state (HRS), wherein the switching ratio is a ratio of current (ILRS) of the dual gated memtransistor at the LRS to that (IHRS) of the dual gated memtransistor at the HRS, and wherein each dual gated memtransistor is configured such that the switching ratio increases with increasing a voltage of the bottom gate electrode.

### Claim 14 (depends on 13)

The crossbar array of claim 13, wherein the 2D semiconductor material comprises MoS2, MoSe2, WS2, WSe2, InSe, GaTe, black phosphorus (BP), or related two-dimensional materials.

### Claim 15 (depends on 13)

The crossbar array of claim 13, wherein the bottom gate electrode layer comprises a globe bottom gate electrode capacitively coupled with the M columns and the N rows of channels.

### Claim 16 (depends on 13)

The crossbar array of claim 13, wherein the bottom gate electrode layer comprises N bottom gate electrodes crossing over the M+1 source-drain electrodes along the row direction, such that each bottom gate electrode is capacitively coupled with M channels of a respective channel row.

### Claim 17 (depends on 13)

The crossbar array of claim 13, wherein the top gate electrodes and the bottom gate electrode layer and the source-drain electrodes comprise a same conductive material or different conductive materials.

### Claim 18 (depends on 17)

The crossbar array of claim 17, wherein each of the top gate electrode and the bottom gate electrode and the source-drain electrodes is formed of gold (Au), titanium (Ti), aluminum (Al), nickel (Ni), chromium (Cr), and other conductive materials.

### Claim 19 (depends on 17)

The crossbar array of claim 17, wherein the bottom gate electrodes are formed of doped silicon (Si).

### Claim 20 (depends on 13)

The crossbar array of claim 13, wherein the top dielectric layer and the bottom dielectric layer comprise a same dielectric material or different dielectric materials.

### Claim 21 (depends on 20)

The crossbar array of claim 20, wherein the top dielectric layer is formed of Al2O3, HfO2, ZrO2, or ZnO.

### Claim 22 (depends on 20)

The crossbar array of claim 20, wherein the bottom dielectric layer is formed of SiO2, or dielectrics including alumina, hafnia, or zirconia.

### Claim 23 (depends on 13)

The crossbar array of claim 13, wherein each memtransistor is configured to have bipolar resistive switching characteristics at different biases applied to the bottom gate electrode with the top gate electrode left floating.

### Claim 24 (depends on 13)

The crossbar array of claim 13, wherein each memtransistor is configured to have a memristive loop with minimal bottom gate bias hysteresis.

### Claim 25 (depends on 13)

The crossbar array of claim 13, wherein each memtransistor is configured such that both long-term potentiation (LTP) and long-term depression (LTD) are operably modulated as a function of a gate bias during writing, while an output current during reading is operably controlled as a function of the gate bias during reading without affecting an intrinsic state of said memtransistor.

### Claim 26 (depends on 13)

The crossbar array of claim 13, wherein the source and drain electrodes (Si/Di+1) are shared by neighboring memtransistors in columns i and i+1 (except i=1, M).

### Claim 27 (depends on 13)

The crossbar array of claim 13, being configured such that each memtransistor is writable and readable independently, thereby minimizing sneak current in the crossbar array.

### Claim 28 (depends on 13)

The crossbar array of claim 13, being configured such that application of a predetermined bottom gate voltage suppresses read currents without changing non-volatile memristive resistance states of the memtransistors in the crossbar array, thereby enabling isolation of the non-volatile memristive resistance states and read currents without additional elements at each node for crossbar operation in the crossbar array.

### Claim 29 (depends on 13)

The crossbar array of claim 13, wherein each memtransistor has gate tunability.

### Claim 30 (depends on 29)

The crossbar array of claim 29, wherein a linear and symmetric learning behavior that produces efficient training of an artificial neural network (ANN) is achievable by the gate tunability.

### Claim 31 (depends on 13)

A circuitry, comprising one or more crossbar arrays according to claim 13.

### Claim 32 (depends on 13)

An electronic device, comprising one or more crossbar arrays according to claim 13.

### Claim 33 (depends on 1)

The memtransistor of claim 1, wherein the memtransistor is configured to have a pinched hysteresis loop in the clockwise direction at forward bias.

### Claim 34 (depends on 33)

The memtransistor of claim 33, wherein the memtransistor is configured to have drain current at the forward bias being larger than that at reverse bias.

### Claim 35 (depends on 1)

The memtransistor of claim 1, wherein the memtransistor is configured such that a top gate voltage controls the switching ratio in a non-monotonic fashion.

### Claim 36 (depends on 1)

The memtransistor of claim 1, wherein the channel has a channel length of about 0.9 μm, and a channel width of about 0.7 μm.

### Claim 37 (depends on 13)

The crossbar array of claim 13, wherein each channel has a channel length of about 0.9 μm, and a channel width of about 0.7 μm.