# US 12,183,810 B2 · Semiconductor devices and methods of manufacture

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- Number: US 12,183,810 B2
- Document ID: US12183810B2
- Status: Granted
- Kind: B2
- Application number: 18/447,489
- Filed: 2023-08-10
- Published: 2023-11-30
- Granted: 2024-12-31
- Earliest claimed: 2021-04-08
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Wei-Chih Kao; Hsin-Che Chiang; Chun-Sheng Liang; Kuo-Hua Pan
- Web page: https://patentgrep.com/patent/US12183810B2

## CPC

- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A dummy fin described herein includes a low dielectric constant (low-k or LK) material outer shell. A leakage path that would otherwise occur due to a void being formed in the low-k material outer shell is filled with a high dielectric constant (high-k or HK) material inner core. This increases the effectiveness of the dummy fin to provide electrical isolation and increases device performance of a semiconductor device in which the dummy fin is included. Moreover, the dummy fin described herein may not suffer from bending issues experienced in other types of dummy fins, which may otherwise cause high-k induced alternating current (AC) performance degradation. The processes for forming the dummy fins described herein are compatible with other fin field effect transistor (finFET) formation processes and are be easily integrated to minimize and/or prevent polishing issues, etch back issues, and/or other types of semiconductor processing issues.

## Claims

### Claim 1

A semiconductor device, comprising:
a plurality of source or drain regions;
a plurality of active fins associated with the plurality of source or drain regions; and
a dummy fin between the plurality of active fins,
wherein the dummy fin comprises:
a high dielectric constant (high-k) material core; and
a low dielectric constant (low-k) material shell surrounding the high-k material core along at least a portion of the dummy fin,
wherein at least a portion of the low-k material shell extends above and below the high-k material core.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a width of the dummy fin is in a range of approximately 5 nanometers to approximately 15 nanometers.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein a height of the dummy fin is in a range of approximately 50 nanometers to approximately 70 nanometers; and
wherein a width of the high-k material core is in a range of approximately 1 nanometer to approximately 3 nanometers.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein a portion of the high-k material core is not covered by the low-k material shell in a top portion of the dummy fin.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein a width of the portion of the high-k material core that is not covered by the low-k material shell in the top portion of the dummy fin is less than a width of the portion of the dummy fin; and
wherein the portion of the high-k material core that is not covered by the low-k material shell in the top portion of the dummy fin occupies less surface area of the top portion of the dummy fin than the low-k material shell.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the high-k material core comprises at least one of:
a high-k oxide,
a high-k nitride, or
a high-k oxy-nitride; and
wherein the low-k material shell comprises:
a low-k oxide,
a low-k nitride
a low-k carbon, or
a low-k combination of oxide, carbon, and nitride.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the low-k material shell completely surrounds the high-k material core along at least a portion of the dummy fin under a gate of the semiconductor device.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the low-k material shell surrounds the high-k material core on three sides of the high-k material core along at least another portion of the dummy fin that is not under the gate.

### Claim 9

A semiconductor device, comprising:
a plurality of active fins extending from a substrate;
a plurality of epitaxial regions associated with the plurality of active fins; and
a dummy fin between the plurality of active fins and the plurality of epitaxial regions,
wherein the dummy fin comprises:
a first dielectric material; and
a second dielectric material, having a lower dielectric constant than the first dielectric material, surrounding the first dielectric material,
wherein at least a portion of the first dielectric material extends above and below the second dielectric material.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, further comprising:
a shallow trench isolation (STI) region between the plurality of active fins.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the STI region comprises a dielectric material.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the dielectric material is silicon oxide.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein the plurality of epitaxial regions resides over the plurality of active fins.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein a first portion of the plurality of epitaxial regions reside in the plurality of active fins, and wherein a second portion of the plurality of epitaxial regions extend beyond the plurality of active fins.

### Claim 15

A semiconductor device, comprising:
a plurality of active fins extending in a first direction;
one or more gates extending in a second direction perpendicular to the first direction;
a plurality of epitaxial regions, associated with the plurality of active fins, extending in the first direction; and
a dummy fin, between the plurality of active fins, extending in the first direction,
wherein the dummy fin comprises:
a first dielectric material; and
a second dielectric material, having a lower dielectric constant than the first dielectric material, surrounding the first dielectric material,
wherein at least a portion of the first dielectric material extends above and below the second dielectric material.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the active fins extend from a substrate.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the one or more gates are within a substrate.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein the plurality of epitaxial regions are not covered by the one or more gates.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, wherein the plurality of active fins are covered by the one or more gates.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, wherein the one or more gates surrounds at least three sides of each of the plurality of active fins, and wherein the plurality of epitaxial regions are included on a portion of the plurality of active fins not covered by the one or more gates.